SA7121A
FUNCTIONAL DESCRIPTION
The circuit is built up out of several functional blocks,
control logic, coil interface, the power-on reset, and the
memory module (EEPROM). The chip activates
automatically during power-up as a result of the built in
power-on reset.
locked in that way. This gives OTP (One Time
Programmable)security.
Memory map
The flexibility of programming allows custom memory
mapping.
Coil Interface
Control logic
Power is derived from a full wave rectifier bridge. Data
modulation takes place by loading the coil inputs to the
bridge with a modulating circuit. The coil interface
includes on-chip high voltage protection. The system
clock for the chip is derived by means of a clock extractor
coupled to the rectifier circuit. The Clock extractor /
prescaler is the time base generator for data reading.
Data is read from the EEPROM to the coil interface
where the rf signal is modulated by the data in the
Manchester coded m ode.
The control logic gets its clock from the clock extractor /
prescaler and facilitates the reading of the data stored in
the data EEPROM.
TIMING SPECIFICATIONS
The COIL1 and COIL2 pads modulate the incoming rf
signal with Manchester encoded data. The data will
repeatedly be read out serially until the power is reduced
sufficiently to activate the power on reset again. There
are 64 rf carrier cycles for each data bit. This is the
nominal setting. An optional setting of 32 rf cycles per bit
can be selected during wafer manufacture.
Memory Array
Data storage:
The data EEPROM is arranged in an 16X8 bit array
composed of 16 columns of 8 bit bytes. The 128 bits of
data stored in the array can be configured in any way as
agreed with the client, and is factory programmed and
n = 64 RF clock cycles per data bit
RF CLOCK
CL0
CL1
CL2
CL3
CL4
CL5
CL6
CL7
CL8
CLn-3
CLn-2
CLn-1
DATA
Dn-1
Dn
Dn+1
DATA OUTPUT
Data output takes place according to Manchester encoding.
DATA
NO
NO
DATA
DATA2 DATA3 DATA4
DATA 0 DATA1
DATA5 DATA6 DATA7
DATA
0
1
0
1
0
1
1
0
MANCHESTER
NO
DATA
NO
DATA
DATA2 DATA3 DATA4
DATA 0 DATA1
DATA5 DATA6 DATA7
0
1
0
1
0
1
1
0
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