SA2532KA/B
Power On Reset
The on chip power on reset circuit monitors the
supply voltage (VDD).
approx. 1.2V, a power on reset occurs to assure
correct start-up and the LNR register is cleared.
Speech Circuit
The speech circuit consists of a transmit and a
receive path with soft clip, mute, line loss
compensation and side tone cancellation.
When VDD rises above
Transmit
DC Conditions
The gain of the transmit path is 35 dB for M1/M2 to
LS (see test circuit in Figure 5). The microphone
input is differential with an input impedance of 25
kOhms. The soft clip circuit limits the output
The normal operating range is from 15mA to 100
mA. Operating range with reduced performance is
from 5mA to 15mA. In the operating range all
functions are operational. In the line hold range
from 0 to 5 mA the device is in a power down mode
and the voltage at LI is reduced to maximum 3.5V.
The dc characteristic (excluding diode bridge and
Pulsing transistors) is determined by the voltage at
LI and the resistor R1 as follows:
voltage at LI to 2.0VPEAK
.
The attack time is
30us/6dB and the decay time is 20 ms/6 dB. When
mute is active, during dialling or after pressing the
MUTE key, the gain is reduced by > 60 dB.
Receive
The receive input is the differential signal of RI and
STB. The gain of the receive path is 2 dB (see test
circuit in Figure 5) with differential outputs,
RO1/RO2 . When mute is active during dialling the
gain is reduced by > 60dB. During DTMF dialling a
MF comfort tone is applied to the receiver. The
comfort tone is the DTMF signal with a level that is
-30dB relative to the line signal.
VLS = VLI + I
.R1
Line
The voltage at LI is 4.5V.
Side Tone
During pulse dialling the speech circuit and other
parts of the device not required are in a power
down mode to save current. The CS pin is pulled to
VSS in order to turn the external shunt transistor on
to keep a low voltage drop at the LS pin during
make periods.
Side Tone is controlled along with Return Loss by a
Double Balance Bridge as shown in Figure 3. Good
sidetone cancellation is achieved by using the
following equation:
Zbal
------ = ----
Zline R1
R5
AC Impedance
The Characteristic or Output impedance of the
SA2532K is set within the IC and adjusted to 600
Ohms. A capacitor may be added to the circuit at
pin CI to add a reactive element and make the
output impedance complex.
The side tone cancellation signal is applied to the
STB input.
Oscillator
Line Loss Compensation
All the Timing Functions of the SA2532K are based
on a Clock Frequency of 3.58MHz. A ceramic
resonator of this frequency should be connected to
the OSC pin. In practice minor deviations from the
nominal frequency may occur due to the
characteristics of the frequency reference device
used and so it is recommended that care is taken in
the selection of components. Typically a small
value capacitor ( ≤ 47pF) may be required to be
connected in parallel with the Frequency Reference
to ensure start-up and/or operation at the nominal
frequency.
The line loss compensation is a pin selectable
option. When it is activated, the gains of the
transmit and receive amplifiers are changed by 6dB
in accord with the DC conditions as measured at
Pins LI and LS. When the LLC pin is low the
adjustment in gain occurs over the range ILINE = 20
to 50mA. When the LLC pin is high the gain range
is ILINE = 45 to 75mA.. Note that these values apply
for R1 = R30 Ω. When LLC pin is open then the
amplifier gains remain fixed regardless of the line
current (see figure 6 and figure 7).
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