LM358DR/PWR/DGKR,LM2904DR/PWR/DGKR/VQDR/VQPWR
LM324DR/PWR/KDR,LM2902DR/PER/KDR/KPWR/KVQDR/KVQPWR
●Circuit
Diagram
Vcc
Technical Note
IN-
OUT
IN+
GND
Fig.97 Circuit Diagram (each Op-Amp)
●Measurement
Circuit 1 NULL Method Measurement Condition
Measurement item
Input Offset Voltage
Input Offset Current
Input Bias Current
Large Signal Voltage Gain
Common-mode Rejection Ratio
Supply Voltage Rejection Ratio
VF
S1
S2
S3
LM358/LM324 family
Vcc
5
5
5
15
15
5
5
5
30
GND
0
0
0
0
0
0
0
0
0
0
EK
‐1.4
‐1.4
‐1.4
‐1.4
‐1.4
-11.4
‐1.4
‐1.4
‐1.4
‐1.4
VICR
0
0
0
0
0
0
0
3.5
0
0
Vcc,GND,EK,VICR Unit:[V]
LM2904/LM2902 family
Calculation
Vcc GND EK VICR
5 to 30
5
5
5
15
15
5
5
5
30
0
0
0
0
0
0
0
0
0
0
‐1.4
‐1.4
‐1.4
‐1.4
‐1.4
-11.4
‐1.4
‐1.4
‐1.4
‐1.4
0
0
0
0
0
0
0
3.5
0
0
1
2
3
4
5
6
VF1 ON ON OFF 5 to 30
VF2 OFF OFF OFF
VF3 OFF ON
VF4 ON OFF
VF5
VF6
VF7
VF8
VF9
VF10
ON
ON
ON
OFF
ON ON
ON OFF
ON OFF
－Calculation－
1.Input Offset Voltage (VIO)
Vio
�½
VF1
1+ Rf /Rs
[V]
0.1[μF]
2. Input offset current (IIO)
Iio
�½
VF2 - VF1
Ri (1+ Rf / Rs)
[A]
S1
Rs
VICR
Ri
Vcc
Rf
50[kΩ]
500[kΩ]
VOUT EK
0.1[μF]
3.Input Bias Current (IIB)
[A]
Ib
�½
2× Ri (1+ Rf / Rs)
VF4 - VF3
+15[V]
500[kΩ]
DUT
S3
1000[pF]
GND
RL
-15[V]
50[Ω] 10[kΩ]
50[Ω] 10[kΩ]
Rs
Ri
S2
Rf
50[kΩ]
4.Large Signal Voltage Gain (AVD)
10× (1+ Rf /Rs) [dB]
AV
�½
20× Log
VF6 - VF5
V
VF
5.Common-mode rejection ratio (CMRR)
CMRR
�½
20× Log
3.5× (1+ Rf/ Rs)
VF8-VF7
[dB]
6.Supply Voltage rejection ratio (KSVR)
PSRR
=
20×Log
△
Vcc×(1+Rf/Rs)
VF10 - VF9
[dB]
Fig.98 Measurement Circuit 1 (each Op-Amp)
△
Vcc=25V
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12/17
2011.06 - Rev.B
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