BR24L□□-W Series,BR24S□□□-W Series
Technical Note
●I
2
C BUS communication
○I
2
C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
2
and acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices
connected by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
SCL
1-7
S
START ADDRESS
condition
8
9
1-7
8
9
1-7
8
9
P
STOP
condition
R/W
ACK
DATA
ACK
DATA
ACK
Fig.35 Data transfer timing
○Start
condition (Start bit recognition)
・Before
executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This
IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop
condition (stop bit recongnition)
・Each
command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge
(ACK) signal
・This
acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The
device (this IC at slave address input of write command, read command, and
μ-COM
at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This
IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each
write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each
read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device
addressing
・Output
slave address after start condition from master.
・The
significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next
slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The
most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is
as shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
1 0 1
1 0 1
1 0 1
1 0 1
1 0 1
1 0 1
1 0 1
Slave address
0
0
0
0
0
0
0
A2 A1 A0
A2 A1 A0
A2 A1 PS
A2 P1 P0
P2 P1 P0
A2 A1 A0
A2 A1 A0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
―
―
―
―
―
―
―
Maximum number of
connected buses
8
8
4
2
1
8
8
PS, P0�½�P2 are page select bits.
Note) Up to 4 units BR24L04-W, up to 2 units of BR24L08-W, and one unit of BR24L16-W can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
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2009.09 - Rev.D
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