BR24Lxxx-W Series (1K 2K 4K 8K 16K 32K 64K)
●Sync
data input / output timing
tR
SCL
tHD:STA
SDA
(入力)
(input)
tBUF
(出力)
(output)
SDA
tPD
tDH
tSU:DAT
tLOW
tHD:DAT
tF
tHIGH
Datasheet
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Figure 1-(b) Start-stop bit timing
SCL
SCL
SDA
DATA(1)
D1
D0
ACK
DATA(n)
ACK
�½�WR
SDA
D0
Write data
ACK
�½�W
R
Stop condition
Start condition
WP
Stop condition
ストップコンディション
(n-th
address)
tSU：WP
�½�HD：WP
Figure 1-(c) Write cycle timing
SCL
DATA(1)
SDA
D1
D0
ACK
tHIGH:WP
WP
DATA(n)
ACK
tWR
Figure 1-(d) WP timing at write execution
○At
write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By
setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
www.rohm.com
©2012 ROHM Co., Ltd. All rights reserved.
TSZ22111�½�15�½�001
4/36
TSZ02201-0R2R0G1000290-1-2
21.AUG.2012 Rev.001
ROHM [ ROHM ]
