BM28723AMUV
Description of Function - continued
15 Setting and Reading Method of BQ
It explains a detailed sequence of the setting method and the reading method of BQ separately for usage.
15.1 BQ coefficient setting
BQ consists of Bi-quad filter as follows. Each coefficient b0, b1, b2, a1, and a2 of BQ can be written directly.
It is S2.21 format, and setting range is -4≤x<+4.
Moreover, the coefficient address is shown in Table 1.
The output of multipliers and the adder might exceed +48dB by the
coefficient of a1, a2, b0, b1, and b2. In that case, data becomes
saturation output. Therefore, the output of the filter cannot obtain
the aimed characteristic.
X[n]
Y[n]
b0
b1
b2
Z-1
Z-1
Z-1
X[n-1]
a1
a2
Y[n-1]
Z-1
X[n-2]
Y[n-2]
-1 is multiplied by the coefficient of a1 and a2.
Considering efficiency of calculation at DSP.
Direct form 1
Figure 63
15.2 Writing sequence (Set in numerical order)
1. Address setting (0x61) Refer to Table 1.
2. 24bit coefficient upper [23:16] bit setting (0x62[7:0])
3. 24bit coefficient middle [15:8] bit setting (0x63[7:0])
4. 24bit coefficient lower [7:0] bit setting (0x64[7:0])
5. The writing of coefficients is performed. (0x65[0]=0x1)
Caution 1: After completion of writing coefficients this register is cleared automatically.
It is not necessary to write 0x65[0]=0x0. Coefficient writing takes about 100μs.
Caution 2: 100μs should not change an address setup and 24-bit coefficient setup after coefficient write-in execution.
(ex) When 0x3DEDE7 is written, same L/Rch, 12band BQ1 b0
1. 0x61=0x00 (12band BQ1 b0 is appointed)
2. 0x62=0x3D (Upper [23:16] is setting)
3. 0x63=0xED (Middle [15:8] is setting)
4. 0x64=0xE7 (Lower [7:0] is setting)
5. 0x65=0x01 (Coefficient transfer)
6. 100μs or more wait
15.3 Read-back sequence (Set in numerical order)
1. Address setting (0x61) Refer to Table 1.
2. Setting of a read-back register address (0xD0) Refer to P.22 “5 Reading of Data”
3. Read-back of the 24bit coefficient upper [23:16] bit (0x66[7:0])
4. Read-back of the 24bit coefficient middle [15:8] bit (0x67[7:0])
5. Read-back of the 24bit coefficient lower [7:0] bit (0x68[7:0])
15.4 When the coefficient of BQ is set up directly and a soft transition is performed
1. Set BQ coefficient to soft transition addresses. The addresses are 0x50 to 0x54. Please refer to Table1.
Since in the case of 0x60[4]=0x1 (Enable L/R independent setting) and 0x53[5:4]=0x0 a soft transition is carried out
and it is set to LR simultaneously, please write a coefficient in both LR address.
In the case of 0x53[5:4]=0x1, coefficient is set to only Lch address.
In the case of 0x53[5:4]=0x2, coefficient is set to only Rch address.
2. Select BQ Band that is performed soft transition by setting 0x51[4:0] address.
(Refer to chapter 14.4 Bi-quad Type Filter)
3. 0x58[0]=0x1, Start soft transition (After the completion of soft transition this register is automatically cleared 0x0.)
4. Wait soft transition completion, or read command 0x59[0], and wait until it 0x59[0] cleared (0x0).
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TSZ02201-0C1C0E900720-1-2
31.Aug.2018 Rev.001
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