BD52□□G, BD52□□FVE, BD53□□G, BD53□□FVE series
Technical Note
Setting of Detector Delay Time
This detector IC can be set delay time at the rise of V
DD
by the capacitor connected to CT terminal.
Delay time at the rise of V
DD
T
PLH
：Time
until when Vout rise to 1/2 of V
DD
after V
DD
rise up and beyond the release
voltage(V
DET
+∆V
DET
)
T
PLH
= -C
CT
×R
CT
×ln
C
CT
:
V
CTH
:
V
DD
-V
CTH
V
DD
CT pin Externally Attached Capacitance
CT pin Threshold Voltage（P.2 V
CTH
refer.）
R
CT
: CT pin Internal Impedance
（P.2
R
CT
refer.）
Ln : Natural Logarithm
Reference Data of Falling Time (T
PHL
) Output
Examples of Falling Time (T
PHL
) Output
Part Number
tPHL[µs] -40°C
tPHL[µs] ,+25°C
tPHL[µs],+105°C
BD5227G
30.8
30
28.8
BD5327G
26.8
26
24.8
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD52□□G/FVE series uses an open drain
output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in
this case becomes VDD or the voltage of the other power supply].
V
DD
V
DD
R1
Vref
V
OUT
R2
Q3
R3
GND
CT
GND
CT
R3
Q1
R2
Q3
Q1
R
L
RESET
Vref
V
DD
R1
V
DD
RESET
V
OUT
Q2
Fig.15 (BD52□□Type Internal Block Diagram)
Fig.16 (BD53□□Type Internal Block Diagram)
Timing Waveforms
Example: the following shows the relationship between the input voltage V
DD
, the CT Terminal Voltage V
CT
and the output
voltage V
OUT
when the input power supply voltage V
DD
is made to sweep up and sweep down (The circuits are those in
Fig.15 and 16).
1
When the power supply is turned on, the output is unsettled from
V
DD
after over the operating limit voltage (V
OPL
) until T
PHL
. There fore it is
possible that the reset signal is not outputted when the rise time of
V
DET
+ΔV
DET
⑤
V
DET
VDD is faster than T
PHL
.
2
When V
DD
is greater than V
OPL
but less than the reset release
V
OPL
0V
voltage (V
DET
+∆V
DET
), the CT terminal (V
CT
) and output (V
OUT
)
voltages will switch to L.
V
CT
3
If V
DD
exceeds the reset release voltage (V
DET
+∆V
DET
), then
1/2 V
DD
V
OUT
switches from L to H (with a delay to the CT terminal).
4
If V
DD
drops below the detection voltage (V
DET
) when the power
supply is powered down or when there is a power supply fluctuation,
V
OUT
switches to L (with a delay of T
PHL
).
V
OUT
T
PLH
T
PHL
T
PLH
5
The potential difference between the detection voltage and the
T
PHL
release voltage is known as the hysteresis width (∆V
DET
). The
system is designed such that the output does not flip-flop with power
① ②
③ ④
supply fluctuations within this hysteresis width, preventing
malfunctions due to noise.
Fig.17
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2009.06 - Rev.B
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