ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ
ꢀꢋ ꢁꢈ ꢄ ꢌ ꢊ ꢍꢋꢁ ꢎꢏꢐ ꢎꢑ ꢀꢋ ꢐ ꢋꢅꢌ ꢍꢑ ꢒ ꢈ ꢓꢐꢌ
SCES219N − APRIL 1999 − REVISED JUNE 2005
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
I
Supports Partial-Power-Down Mode
off
Operation
D
D
D
D
D
Supports 5-V V
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
CC
Inputs Accept Voltages to 5.5 V
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Max t of 3.6 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
CC
24-mA Output Drive at 3.3 V
− 1000-V Charged-Device Model (C101)
YEA, YEP, YZA,
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
OR YZP PACKAGE
(BOTTOM VIEW)
3
2
1
4
5
Y
GND
B
1
2
3
5
A
V
Y
A
B
V
1
2
3
5
CC
CC
1
2
3
5
A
B
V
Y
CC
B
V
A
CC
4
GND
Y
4
GND
4
GND
See mechanical drawings for dimensions.
description/ordering information
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G32 performs the Boolean function Y + A ) B or Y + A • B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
ꢎꢒ ꢑ ꢔꢏ ꢆ ꢐꢋ ꢑ ꢁ ꢔ ꢓꢐꢓ ꢕꢖ ꢗ ꢘꢙ ꢚ ꢛꢜ ꢕꢘꢖ ꢕꢝ ꢞꢟ ꢙ ꢙ ꢠꢖꢜ ꢛꢝ ꢘꢗ ꢡꢟꢢ ꢣꢕꢞ ꢛꢜ ꢕꢘꢖ ꢤꢛ ꢜꢠ ꢥ
ꢎꢙ ꢘ ꢤꢟꢞ ꢜ ꢝ ꢞ ꢘꢖ ꢗꢘ ꢙ ꢚ ꢜ ꢘ ꢝ ꢡꢠ ꢞ ꢕꢗ ꢕꢞꢛ ꢜꢕ ꢘꢖꢝ ꢡꢠ ꢙ ꢜꢦ ꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢐꢠꢧ ꢛꢝ ꢋꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ
ꢝ ꢜ ꢛ ꢖꢤ ꢛ ꢙꢤ ꢨ ꢛ ꢙꢙ ꢛ ꢖ ꢜꢩꢥ ꢎꢙ ꢘ ꢤꢟꢞ ꢜꢕꢘꢖ ꢡꢙ ꢘꢞ ꢠꢝ ꢝꢕ ꢖꢪ ꢤꢘꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢩ ꢕꢖꢞ ꢣꢟꢤ ꢠ
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
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