MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
PIN CONNECTIONS
CASE 646/CASE 751A/CASE 948G
CASE 510AJ
CASE 626/CASE 751
VCC
1
2
3
4
8
7
6
5
1
Offset Null
Inputs
NC
V
Output 1
Inputs 1
14
13
Output 4
Inputs 4
10
-
+
CC
2
3
4
1
9
8
7
6
1
4
3
Output 2
NC
Output 1
NC
-
+
-
+
Output
12
11
2
V
EE
Offset Null
V
CC
V
EE
3
4
In 2
In 1
(Single, Top View)
5
6
10
9
2
+
-
+
-
Inputs 2
Output 2
Inputs 3
Output 3
In + 1
In + 2
1
2
3
4
8
7
6
5
Output 1
Inputs 1
V
CC
5
Output 2
-
7
8
+
VEE/GND
(Top View)
-
+
Inputs 2
(Quad, Top View)
V
EE
(Dual, Top View)
V
CC
Q3
Q4
Q6
Q5
Q7
Q1
Q17
Q2
R2
R1
C1
D2
Q18
Bias
R6
R7
Q11
Q8
Q9
Q10
Output
-
R8
Inputs
+
C2
D3
Q19
Q15
Q16
Q13
Q14
Base
Current
Cancellation
Q12
D1
Current
Limit
R5
R3
R4
V
EE
/GND
Offset Null
(MC33071, MC34071 only)
Figure 1. Representative Schematic Diagram
(Each Amplifier)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage (from V to V
)
V
S
+44
V
V
EE
CC
Input Differential Voltage Range
Input Voltage Range
V
IDR
(Note 1)
(Note 1)
Indefinite
+150
V
IR
V
Output Short Circuit Duration (Note 2)
Operating Junction Temperature
Storage Temperature Range
t
Sec
°C
°C
V
SC
T
J
T
stg
−60 to +150
ESD Capability, Dual and Quad (Note 3)
Human Body Model
Machine Model
ESD
2000
200
HBM
ESD
MM
1. Either or both input voltages should not exceed the magnitude of V or V
.
CC
EE
2. Power dissipation must be considered to ensure maximum junction temperature (T ) is not exceeded (see Figure 2).
J
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115)
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