DS2154
1 DETAILED DESCRIPTION
The DS2154 enhanced single-chip transceiver (SCT) contains all the necessary functions for connection
to E1 lines. The device is an upward compatible version of the DS2153 single-chip transceiver. The on-
board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The
DS2154 automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to over 2km in length.
The device can generate the necessary G.703 waveshapes for both 75Ω coax and 120Ω twisted cables.
The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit
or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data
stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa bit information.
The device contains a set of internal registers that the user can access to control the operation of the unit.
Quick access via the parallel control port allows a single controller to handle many E1 lines. The device
fully meets all the latest E1 specifications including ITU G.703, G.704, G.706, G.823, G.932, and I.431
as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
1.1 Introduction
The DS2154 is a superset version of the popular DS2153Q E1 single-chip transceiver offering the new
features listed below. All the original features of the DS2153Q have been retained and software created
for the original devices is transferable into the DS2154.
1.1.1 New Features
Option for nonmultiplexed bus operation
Crystal-less jitter attenuation
Additional hardware signaling capability including:
– Receive signaling reinsertion to a backplane multiframe sync
– Availability of signaling in a separate PCM data stream
– Signaling freezing
– Interrupt generated on change of signaling data
Improved receive sensitivity: 0dB to -43dB
Per-channel code insertion in both transmit and receive paths
Expanded access to Sa and Si bits
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192MHz clock synthesizer
Per-channel loopback
Addition of hardware pins to indicate carrier loss and signaling freeze
Line interface function can be completely decoupled from the framer/formatter to allow:
– Interface to optical, HDSL, and other NRZ interfaces
– Ability to “tap” the transmit and receive bipolar data streams for monitoring purposes
– Ability to corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Transmit current limiter to meet the 50mA short circuit requirement
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
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ROCHESTER [ Rochester Electronics ]
