DS2154
Figure 14-5. Transmit Side Timing
NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0).
NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1).
NOTE 4: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT.
NOTE 5: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC4 BEGIN WITH THE ALIGN FRAME.
Figure 14-6. Transmit Side Boundary Timing
NOTE 1: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE Sa4 BITS.
NOTE 5: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT FORMATTER WITH THE
CAS MULTIFRAME ALIGNMENT NIBBLE (0000).
NOTE 4: SHOWN IS A NON-ALIGN FRAME BOUNDARY.
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ROCHESTER [ Rochester Electronics ]
