DS2154
in Table 13-2. The line driver in the DS2154 contains a current limiter that prevents more than 50mA
(RMS) from being sourced in a 1Ω load.
Table 13-2. Transformer Specifications
SPECIFICATION
RECOMMENDED VALUE
1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%
600µH minimum
Turns Ratio
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
1.0µH maximum
40pF maximum
1.2Ω maximum
13.3 Jitter Attenuator
The DS2154 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 13-4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a 2.048MHz clock (±50ppm) must be applied at the MCLK
pin or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a
crystal is applied across the MCLK and XTALD pins, then capacitors should be placed from each leg of
the crystal to the local ground plane as shown in Figure 13-1. On-board circuitry adjusts either the
recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a
smooth jitter-free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to
provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the
incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then
the DS2154 will divide the internal nominal 32.768MHz clock by either 15 or 17 instead of the normal 16
to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter
Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
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ROCHESTER [ Rochester Electronics ]
