DS2154
14 TIMING DIAGRAMS
Figure 14-1. Receive Side Timing
NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0).
NOTE 2: RSYNC IN THE FRAME MODE (RCR1.6 = 0).
NOTE 3: RSYNC IS PROGRAMMED TO PULSE HIGH DURING THE Sa4 BIT POSITION.
NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE Sa BITS AS WELL AS THE REST OF THE RECEIVE DATASTREAM.
NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS WITH THE FAS WORD.
Figure 14-2. Receive Side Boundary Timing (with Elastic Store Disabled)
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 2: RLCLK IS PROGRAMMED TO PULSE HIGH DURING THE Sa4 BITS POSITION.
NOTE 3: SHOWN IS A NON-ALIGN FRAME BOUNDARY.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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ROCHESTER [ Rochester Electronics ]
