DS2154
11 ELASTIC STORES OPERATION
The DS2154 contains dual two-frame (512 bits) elastic stores: one for the receive direction and one for
the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert
the E1 data stream to 1.544Mbps (or a multiple of 1.544Mbps), which is the T1 rate. Secondly, they can
be used to absorb the differences in frequency and phase between the T1 data stream and an
asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544MHz or 2.048MHz). The
backplane clock can burst at rates up to 8.192MHz. Both elastic stores contain full controlled slip
capability, which is necessary for this second purpose. The elastic stores can be forced to a known depth
via the Elastic Store Reset bit (CCR3.4). Toggling the CCR3.4 bit forces the read and write pointers into
opposite frames. Both elastic stores within the DS2154 are fully independent and no restrictions apply to
the sourcing of the various clocks that are applied to them. The transmit side elastic store can be enabled
whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can
interface to either a 1.544MHz or 2.048MHz backplane without regard to the backplane rate the other
elastic store is interfacing.
11.1 Receive Side
If the receive side elastic store is enabled (RCR2.1 = 1), then the user must provide either a 1.544MHz
(RCR2.2 = 0) or 2.048MHz (RCR2.2 = 1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR1.5 = 1) or having the RSYNC pin provide a
pulse on frame/multiframe boundaries (RCR1.5 = 0). If the user wishes to obtain pulses at the frame
boundary, then RCR1.6 must be set to 0; if the user wishes to have pulses occur at the multiframe
boundary, then RCR1.6 must be set to 1. The DS2154 will always indicate frame boundaries via the
RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either CAS
(RCR1.7 = 0) or CRC4 (RCR1.7 = 1) multiframe boundaries will be indicated via the RMSYNC output.
If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then every fourth channel of the
received E1 data will be deleted and an F-bit position (which will be forced to 1) will be inserted. Hence
Channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the
received E1 data stream. Also, in 1.544MHz applications, the RCHBLK output will not be active in
Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 14 for timing details. If the
512-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full
frame of data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the
buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.
11.2 Transmit Side
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544MHz (CCR3.1 = 0) or 2.048MHz (CCR3.1 = 1) clock can be
applied to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192MHz. If the
user selects to apply a 1.544MHz clock to the TSYSCLK pin, then the data sampled at TSER will be
stuffed with eight empty channels. The user must supply an 8kHz frame sync pulse to the TSSYNC input.
See Section 14 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0
bit and the direction of the slip is reported in the RIR.6 and RIR.7 bits.
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ROCHESTER [ Rochester Electronics ]
