ADV7174/ADV7179
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
39
40
38 37 36 35 34 33 32 31
PIN 1
INDICATOR
1
2
30
29
28
27
26
25
24
23
22
21
CLOCK
V
REF
V
AA
DAC A
DAC B
3
P5
P6
4
V
AA
ADV7174/ADV7179
5
GND
P7
LFCSP
TOP VIEW
(Not to Scale)
6
V
GND
GND
GND
GND
AA
7
DAC C
COMP
8
9
SDATA
SCLOCK
10
V
AA
11 12 13 14 15 16 17 18 19 20
Figure 5. Pin Configurations
Table 6. Pin Function Descriptions
Input/
Output
Mnemonic
P7–P0
CLOCK
Function
I
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0). P0 is the LSB.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz
(NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
I/O
HSYNC
(Modes 1 and 2) Control Signal. This pin may be configured to output (master mode) or accept (slave
mode) sync signals.
FIELD/VSYNC I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output
(master mode) or accept (slave mode) these control signals.
BLANK
I/O
I
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
SCRESET/RTC
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a
subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0.
Alternatively, it can be configured as a real-time control (RTC) input.
VREF
RSET
I/O
I
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.
COMP
O
Compensation Pin. Connect a 0.1 μF capacitor from COMP to VAA. For optimum dynamic performance in low
power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF.
DAC A
DAC B
DAC C
SCLOCK
SDATA
ALSB
O
O
O
I
I/O
I
DAC Output (see Table 13)
DAC Output (see Table 13).
DAC Output (see Table 13).
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the MPU address.
RESET
I
This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC
operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled.
TTX
I
Teletext Data.
TTXREQ
VAA
GND
O
P
G
Teletext Data Request Signal/Defaults to GND when Teletext Not Selected.
Power Supply (2.8 V or 3.3 V).
Ground Pin.
Rev. B | Page 10 of 52
ROCHESTER [ Rochester Electronics ]
