ADSP-BF531/ADSP-BF532/ADSP-BF533
0 V to provide the lowest static power dissipation. Any critical
information stored internally (memory contents, register con-
tents, etc.) must be written to a nonvolatile storage device prior
to removing power if the processor state is to be preserved.
Since VDDEXT is still supplied in this mode, all of the external
pins three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to still have
power applied without drawing unwanted current. The internal
supply regulator can be woken up either by a real-time clock
wakeup or by asserting the RESET pin.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before it can transition to the full-on or sleep modes.
Table 4. Power Settings
Power Savings
Core
Clock
System Internal
Clock Power
As shown in Table 5, the processors support three different
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
processor into its own power domain, separate from the RTC
and other I/O, the processor can take advantage of dynamic
power management without affecting the RTC or other I/O
devices. There are no sequencing requirements for the various
power domains.
PLL
Mode
Full On
Active
PLL
Bypassed (CCLK) (SCLK) (VDDINT)
Enabled No
Enabled Enabled On
Enabled Enabled On
Enabled/ Yes
Disabled
Sleep
Enabled
Disabled
—
—
Disabled Enabled On
Disabled Disabled On
Deep
Sleep
Hibernate Disabled
—
Disabled Disabled Off
Table 5. Power Domains
Sleep Operating Mode—High Dynamic Power Savings
Power Domain
VDD Range
VDDINT
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the proces-
sor will transition to the full-on mode. If BYPASS is enabled, the
processor will transition to the active mode.
VDDRTC
VDDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full-
on mode.
The power savings factor is calculated as:
power savings factor
2
fCCLKRED
---------------------
fCCLKNOM
VDDINTRED
--------------------------
VDDINTNOM
tRED
----------
tNOM
=
where the variables in the equation are:
Hibernate State—Maximum Static Power Savings
f
f
V
V
CCLKNOM is the nominal core clock frequency
CCLKRED is the reduced core clock frequency
DDINTNOM is the nominal internal supply voltage
DDINTRED is the reduced internal supply voltage
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to
the FREQ bits of the VR_CTL register. In addition to disabling
the clocks, this sets the internal power supply voltage (VDDINT) to
Rev. H
| Page 12 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
