ADM1024
Parameter
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
Glitch Immunity
DIGITAL INPUT LOGIC LEVELS
7
(ADD, CI,
RESET,
VID0–VID4, FAN1, FAN2)
Input High Voltage, V
IH
Input Low Voltage, V
IL
NTEST_IN
Input High Voltage, V
IH
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
8
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU; STA
Start Hold Time, t
HD; STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU; DAT
Data Hold Time, t
HD; DAT
Min
Typ
Max
Unit Test Conditions/Comments
2.2
0.8
500
100
V
V
mV
ns
2.2
0.8
2.2
–1
1
20
400
50
1.3
600
600
1.3
0.6
300
300
100
900
V
V
V
µA
µA
pF
kHz
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns
V
CC
= 2.85 V – 5.5 V
V
CC
= 2.85 V – 5.5 V
V
CC
= 2.85 V – 5.5 V
V
IN
= V
CC
V
IN
= 0
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
A
= 25°C and represent most likely parametric norm. Shutdown current typ is measured with V
CC
= 3.3 V.
3
TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including an external series input
protection resistor value between 0 kΩ and 1 kΩ.
4
Total monitoring cycle time is nominally
m
×
755
µs
+
n
×
33244
µs,
where
m
is the number of channels configured as analog inputs, plus 2 for the internal V
CC
measurement and internal temperature sensor, and
n
is the number of channels configured as external temperature channels (D1 and D2).
5
The total fan count is based on two pulses per revolution of the fan tachometer output.
6
Open-drain digital outputs may have an external pull-up resistor connected to a voltage lower or higher than V
CC
(up to 6.5 V absolute maximum).
7
All logic inputs except ADD are tolerant of 5 V logic levels, even if V
CC
is less than 5 V. ADD is a three-state input that may be connected to V
CC
, GND, or left
open-circuit.
8
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.2 V for a rising edge.
Specifications subject to change without notice.
t
R
t
LOW
SCL
t
F
t
HD:STA
t
HD:STA
SDA
t
HD:DAT
t
HIGH
t
SU:DAT
t
SU:STA
t
SU:STO
t
BUF
P
S
S
P
Figure 1. Diagram for Serial Bus Timing
REV. C
–3–
ROCHESTER [ Rochester Electronics ]
