AD9772A
4. The AD9772A digital interface, consisting of edge-triggered
latches and a flexible differential or single-ended clock input,
can support input data rates up to 160 MSPS.
5. An on-chip PLL clock multiplier generates all of the
internal high speed clocks required by the interpolation
filter and DAC.
6. The current output(s) of the AD9772A can easily be
configured for various single-ended or differential circuit
topologies.
PRODUCT HIGHLIGHTS
1. A flexible, low power 2× interpolation filter supporting
reconstruction bandwidths of up to 67.5 MHz can be
configured for a low- or high-pass response with 73 dB
of image rejection for traditional baseband or direct IF
applications.
2. A zero-stuffing option enhances direct IF applications.
3. A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.
Rev. C | Page 3 of 40
ROCHESTER [ Rochester Electronics ]
