AD9708
18
16
14
8
6
4
30
125MSPS
125MSPS
25
20
15
10
100MSPS
100MSPS
12
10
8
50MSPS
50MSPS
6
2
25MSPS
5MSPS
25MSPS
5MSPS
4
5
0
2
0
0
2
4
6
8
10 12 14 16 18 20
– mA
0.01
0.1
RATIO (f
1
0.01
0.1
RATIO (f
1
/f
)
I
/f
)
OUT CLK
OUTFS
OUT CLK
Figure 21. IDVDD vs. Ratio
@ DVDD = 3 V
Figure 19. IAVDD vs. IOUTFS
Figure 20. IDVDD vs. Ratio
@ DVDD = 5 V
FERRITE
BEADS
POWER DISSIPATION
The power dissipation, PD, of the AD9708 is dependent on
several factors, including: (1) AVDD and DVDD, the power
supply voltages; (2) IOUTFS, the full-scale current output; (3)
fCLOCK, the update rate; (4) and the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, IAVDD, and the digital supply current,
IDVDD. IAVDD is directly proportional to IOUTFS, as shown in
AVDD
TTL/CMOS
LOGIC
10-22F
0.1F
100F
CIRCUITS
TANT.
CER.
ELECT.
ACOM
+5V OR +3V
POWER SUPPLY
Figure 19, and is insensitive to fCLOCK
.
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 20 and 21
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
Figure 22. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD9708. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding, current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.
APPLYING THE AD9708
Power and Grounding Considerations
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection
placement and routing and supply bypassing and grounding.
The evaluation board for the AD9708, which uses a four layer
PC board, serves as a good example for the above mentioned
considerations. The evaluation board provides an illustration of
the recommended printed circuit board ground, power and
signal plane layouts.
All analog ground pins of the DAC, reference and other analog
components, should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
Proper grounding and decoupling should be a primary objective
in any high speed system. The AD9708 features separate analog
and digital supply and ground pins to optimize the management
of analog and digital ground currents in a system. In general,
AVDD, the analog supply, should be decoupled to ACOM, the
analog common, as close to the chip as physically possible. Simi-
larly, DVDD, the digital supply, should be decoupled to DCOM
as close as physically as possible.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some “free” capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous
voltage drops in the signal ground paths. It is recommended that
all connections be short, direct and as physically close to the
package as possible in order to minimize the sharing of conduc-
tion paths between different currents. When runs exceed an inch
in length, strip line techniques with proper termination resistor
For those applications requiring a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 22. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
REV. B
–10–
ROCHESTER [ Rochester Electronics ]
