AD96685/AD96687–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = 5.0 V; Negative Supply Voltage = –5.2 V, unless otherwise noted.)
Industrial Temperature Range –25؇C to +85؇C
Test
Level
AD96685BR
AD96687BQ/BP/BR
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Input Offset Voltage
25°C
Full
Full
25°C
Full
25°C
Full
25°C
25°C
Full
I
VI
V
I
VI
I
VI
V
V
VI
VI
1
2
3
1
2
3
mV
mV
µV/°C
µA
Input Offset Drift
Input Bias Current
20
7
20
7
10
13
1.0
1.2
10
13
1.0
1.2
µA
Input Offset Current
0.1
0.1
µA
µA
Input Resistance
200
2
200
2
kΩ
pF
Input Capacitance
Input Voltage Ranges2
Common-Mode Rejection Ratio
–2.5
80
+5.0
–2.5
80
+5.0
V
dB
Full
90
90
ENABLE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Full
Full
Full
Full
VI
VI
VI
VI
–1.1
–1.1
V
V
µA
µA
–1.5
40
5
–1.5
40
5
DIGITAL OUTPUTS3
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
–1.1
–1.1
V
V
–1.5
–1.5
SWITCHING PERFORMANCES
Propagation Delays4
Input to Output HIGH
Input to Output LOW
Latch Enable to Output HIGH
Latch Enable to Output LOW
Dispersions5
25°C
25°C
25°C
25°C
25°C
IV
IV
IV
IV
V
2.5
2.5
2.5
2.5
50
3.5
3.5
3.5
3.5
2.5
2.5
2.5
2.5
50
3.5
3.5
3.5
3.5
ns
ns
ns
ns
ps
Latch Enable
Minimum Pulsewidth
Minimum Setup Time
Minimum Hold Time
25°C
25°C
25°C
IV
IV
IV
2.0
0.5
0.5
3.0
1.0
1.0
2.0
0.5
0.5
3.0
1.0
1.0
ns
ns
ns
POWER SUPPLY6
Positive Supply Current (+5.0 V)
Negative Supply Current (–5.2 V)
Full
Full
Full
VI
VI
VI
8
15
70
9
18
15
31
70
18
36
mA
mA
dB
Power Supply Rejection Ratio7
60
60
NOTES
1RS = 100 Ω.
2Input Voltage Range can be extended to –3.3 V if –VS = –6.0 V.
3Outputs terminated through 50 Ω to –2.0 V.
4Propagation delays measured with 100 mV pulse (10 mV overdrive) to 50% transition point of the output.
5Change in propagation delay from 100 mV to 1 V input overdrive.
6Supply voltages should remain stable within 5% for normal operation.
7Measured at 5% of +VS and –VS.
Specifications subject to change without notice.
COMPARE
LATCH
ENABLE
50%
tS
– Minimum SetupTime
– Minimum Hold Time
– Input to Output Delay
tS
LATCH
tH
tH
tPW(E)
V
DD
DIFFERENTIAL
INPUT
tPD
V
IN
V
VOLTAGE
OS
tPD(E) – LATCH ENABLE to Output Delay
tPD(E)
tPD
tPW(E) – Minimum LATCH ENABLE Pulsewidth
Q
50%
50%
V
– Input OffsetVoltage
– OverdriveVoltage
OS
V
OD
Q
Figure 1. System Timing Diagram
–2–
REV. D
ROCHESTER [ Rochester Electronics ]
