AD9221/AD9223/AD9220
shunt capacitor can help limit the wideband noise at the A/D’s
input by forming a low-pass filter. Note, however, that the
combination of this series resistance with the equivalent input
capacitance of the AD9221/AD9223/AD9220 should be evalu-
ated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where har-
monic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF of
input capacitance to set the filter’s 3 dB cutoff frequency.
disable the reference amplifier if the SENSE pin is tied to AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
AD9221/AD9223/AD9220
TO
A/D
5kꢂ
CAPT
5kꢂ
A2
5kꢂ
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e., VINA
and/or VINB) and analog ground. Since this additional shunt
capacitance combines with the equivalent input capacitance of
the AD9221/AD9223/AD9220, a lower series resistance can
be selected to establish the filter’s cutoff frequency while not
degrading the distortion performance of the device. The shunt
capacitance also acts like a charge reservoir, sinking or sourcing
the additional charge required by the hold capacitor, CH, further
reducing current transients seen at the op amp’s output.
CAPB
5kꢂ
DISABLE
LOGIC
A2
VREF
A1
1V
7.5kꢂ
SENSE
DISABLE
LOGIC
5kꢂ
A1
REFCOM
The effect of this increased capacitive load on the op amp driv-
ing the AD9221/AD9223/AD9220 should be evaluated. To
optimize performance when noise is the primary consideration,
increase the shunt capacitance as much as the transient response
of the input signal will allow. Increasing the capacitance too
much may adversely affect the op amp’s settling time, frequency
response, and distortion performance.
Figure 9. Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9221/AD9223/AD9220 appear on the CAPT and CAPB
pins. For proper operation when using the internal or an external
reference, it is necessary to add a capacitor network to decouple
these pins. Figure 10 shows the recommended decoupling net-
work. This capacitive network performs the following three
functions: (1) along with the reference amplifier, A2, it provides
a low source impedance over a large frequency range to drive
the A/D internal circuitry, (2) it provides the necessary compen-
sation for A2, and (3) it band-limits the noise contribution from
the reference. The turn-on time of the reference voltage appear-
ing between CAPT and CAPB is approximately 15 ms and
should be evaluated in any power-down mode of operation.
REFERENCE OPERATION
The AD9221/AD9223/AD9220 contain an on-board band gap
reference that provides a pin-strappable option to generate
either a 1 V or 2.5 V output. With the addition of two external
resistors, the user can generate reference voltages other than 1 V
and 2.5 V. Another alternative is to use an external reference for
designs requiring enhanced accuracy and/or drift performance.
See Table II for a summary of the pin-strapping options for the
AD9221/AD9223/AD9220 reference configurations.
0.1ꢁF
CAPT
Figure 9 shows a simplified model of the internal voltage reference
of the AD9221/AD9223/AD9220. A pin-strappable reference
amplifier buffers a 1 V fixed reference. The output from the
reference amplifier, A1, appears on the VREF pin. The voltage
on the VREF pin determines the full-scale input span of the
A/D. This input span equals,
AD9221/
10ꢁF
0.1ꢁF
AD9223/
AD9220
CAPB
0.1ꢁF
Figure 10. Recommended CAPT/CAPB Decoupling
Network
Full-Scale Input Span = 2 ϫ VREF
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM, and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec-
tively, in which the input span can be varied between 2 V and
5 V. Note that those samples within the pipeline A/D during
any reference transition will be corrupted and should be
discarded.
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators that monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path
of A1. If the SENSE pin is tied to REFCOM, the switch is
connected to the internal resistor network, thus providing a
VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a
short or resistor, the switch is connected to the SENSE pin. A
short will provide a VREF of 1.0 V while an external resistor
network will provide an alternative VREF between 1.0 V and
2.5 V. The other comparator controls internal circuitry that will
–12–
REV. E
ROCHESTER [ Rochester Electronics ]
