AD652
SVFC Demultiplexer
The demultiplexer needed to separate the combined signals is
shown in Figure 30. A phase-locked loop drives another 4-phase
clock chip to lock onto the reconstructed clock signal. The sync
pulses are distinguished from the data pulses by their shorter
duration. Each falling edge on the multiplex input signal
triggers the one-shot; at the end of this one-shot pulse, the
multiplex input signal is sampled by a D-type flip-flop. If the
φ
φ
1
2
φ
φ
3
4
1MULTIPLEX
OUTPUT
Q
signal is high, the pulse was short (a sync pulse) and the
output of the D-flop goes low. The D-flop is cleared a short time
(two gate delays) later, and the clock is reconstructed as a
stream of short, low-going pulses. If the multiplex input is a data
pulse, then the signal will still be low and no pulse will appear at
the reconstructed clock output when the D-flop samples at the
end of the one-shot period. See Figure 29.
φ
1
φ
2
φ
3
φ4
SYNC
DATA
Figure 28. Multiplexer Waveforms
If it is desired to recover the individual frequency signals, the
multiplex input is sampled with a D-flop at the appropriate
time, as determined by the rising edge of the various phases
generated by the clock chip. These frequency signals can be
counted as a ratio relative to the reconstructed clock, so it is not
even necessary for the transmitter to be crystal-controlled as
shown in Figure 30.
MULTIPLEX
INPUT
ONE SHOT
RECONSTRUCTED
CLOCK
φ
1
(PHASE LOCKED TO
RECONSTRUCTED
CLOCK)
Figure 29. Demultiplexer Waveforms
+5V
14
RECONSTRUCTED
CLOCK OUTPUT
13
4
5
10
MPX
INPUT
3.01kΩ
1
3
+5V
D
1/2 '74
Q
PHASE LOCK LOOP
MC4044
9
CLOCK CLEAR
719Ω
0.1µF
3
6
16 15 11
4
2
11
8
'00
4
5
VCO
'LS629
2
50pF
1kΩ
'00
8
9
7
+5V
150Ω
390pF
+5V
+5V
TIM 9904A
4 PHASE CLOCK
ONE SHOT
'121
130Ω
V
1
2
3
4
5
6
7
8
9
TANK 1
20
CC
V
Q
CC
1
2
3
4
5
6
7
14
13
19
18
17
16
15
14
13
12
11
TANK 2
GND 1
FFQ
XTAL 2
XTAL 1
NC
A1
NC
2kΩ
12 NC
R
OSCIN
/C
A2
EXT EXT
11
10
9
50pF
EXT
FFD
OSCOUT
C
+5V
φ
φ
φ
φ
4 TTL
φ
φ
2 TTL
1 TTL
R
Q
GND
INT
Q
Q
3 TTL
8
NC
V
φ
φ
3
4
3
4
DD
φ
φ
1
2
φ
1
2
'74 (1/2)
'74 (1/2)
'74 (1/2)
10 GND 2
φ
D
D
D
φ
2
φ
3
φ4
CLOCK
Q
CLOCK
Q
CLOCK
Q
f2
f3
RECONSTRUCTED
FREQUENCY OUTPUTS
f4
NC = NO CONNECT
Figure 30. SVFC Demultiplexers
Rev. C | Page 20 of 28
ROCHESTER [ Rochester Electronics ]
