AD574A
Figure 7 shows a complete timing diagram for the AD574A con-
vert start operation. R/C should be low before both CE and CS
are asserted; if R/C is high, a read operation will momentarily
occur, possibly resulting in system bus contention. Either CE or
CS may be used to initiate a conversion; however, use of CE is
recommended since it includes one less propagation delay than
CS and is the faster input. In Figure 7, CE is used to initiate the
conversion.
Table III. Read Timing—Full Control Mode
Symbol Parameter
Min Typ Max Units
1
tDD
tHD
tHL
Access Time (from CE)
200 ns
Data Valid After CE Low
Output Float Delay
CS to CE Setup
25
ns
2
100 ns
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
150
0
ns
ns
ns
ns
ns
ns
R/C to CE Setup
AO to CE Setup
150
50
0
CS Valid After CE Low
R/C High After CE Low
AO Valid After CE Low
50
NOTES
1tDD is measured with the load circuit of Figure 9 and defined as the time
required for an output to cross 0.4 V or 2.4 V.
2tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 10.
Figure 7. Convert Start Timing
Once a conversion is started and the STS line goes high, convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers cannot be enabled during
conversion.
a. High-Z to Logic 1
Figure 9. Load Circuit for Access Time Test
b. High-Z to Logic 0
Figure 8 shows the timing for data read operations. During data
read operations, access time is measured from the point where
CE and R/C both are high (assuming CS is already low). If CS
is used to enable the device, access time is extended by 100 ns.
a. Logic 1 to High-Z b. Logic 0 to High-Z
Figure 10. Load Circuit for Output Float Delay Test
“STAND-ALONE” OPERATION
The AD574A can be used in a “stand-alone” mode, which is
useful in systems with dedicated input ports available and thus
not requiring full bus interface capability.
In this mode, CE and 12/8 are wired high, CS and AO are wired
low, and conversion is controlled by R/C. The three-state buff-
ers are enabled when R/C is high and a conversion starts when
R/C goes low. This allows two possible control signals—a high
pulse or a low pulse. Operation with a low pulse is shown in
Figure 11. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/C and return
Figure 8. Read Cycle Timing
In the 8-bit bus interface mode (12/8 input wired to DIGITAL
COMMON), the address bit, AO, must be stable at least 150 ns
prior to CE going high and must remain stable during the entire
read cycle. If AO is allowed to change, damage to the AD574A
output buffers may result.
Figure 11. Low Pulse for R/C—Outputs Enabled After
Conversion
REV. B
–9–
ROCHESTER [ Rochester Electronics ]
