RS5C314
Write Data
3.
Writing data to the real-time clock requires inputting setting data (control bits and address bits) to the SIO pin and
then establishing the write mode by using a control bit R/W in the same manner as in read operation.
)
Control bits and address bits are described in the previous section on read cycle.
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• Data bits
D3 to D0 : inputs writing data to the counter or the register describing the functions in order of
MSB to LSB.
3.1 Write Cycle Flow
1. The CE pin is switched from the low level to the high level.
2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this
time, control bits R/W and DT are set equally to 0 while a control bit AD is set to 1 (at the shift clock pulses
1A to 8A from the SCLK pin).
3. Four control bits and four bits of data to be written are input in the descending order of their significance. At
this time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1 (at the shift clock pulses
1B to 8B from the SCLK pin).
4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the
same manner as at the shift clock pulse 1A.
5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the rising edge of the fifth
shift clock pulse and later from the SCLK pin) or the CE pin is switched from the high level to the low level (after
tCEH from the rising edge of the eighth shift clock pulse from the SCLK pin).
CE
1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B 1C 2C 3C
SCLK
Reading from shift register
Input to
SIO pin
AD DT A3 A2 A1 A0
R/W AD DT D3 D2 D1 D0
AD
R/W
R/W
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Control bits
Address bits
Control bits
Data bits
Output from
SIO pin
(Hi-z)
(Hi-z)
(Internal processing)
Setting of
control bits
Writing to
address register
Setting of
control bits
End of write operation
)
In the above figure, the “ ” mark indicates arbitrary data; and the diagonally shaded area indicates the high or low level.
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RICOH COMPANY, LTD.
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