RT9170
The final operating junction temperature for any set of
conditions can be estimated by the following thermal
equation :
EN
NC
PD (MAX) = ( TJ (MAX) - TA ) / θJA
Where TJ (MAX) is the maximum junction temperature of
the die (125°C) and TA is the maximum ambient
temperature. The junction to ambient thermal resistance
(θJA)for SOT-23-3 and SOT-23-5 packages at recommended
minimum footprint is 250°C/W, 175°C/W for SOT-89
package (θJA is layout dependent). Visit our website in
which “Recommended Footprints for Soldering Surface
Mount Packages” for detail.
VOUT
VIN
GND
PCB Layout
SOT-23-5 Board Layout
Good board layout practices must be used or instability
can be induced because of ground loops and voltage
drops. The input and output capacitors MUST be directly
connected to the input, output, and ground pins of the
device using traces which have no other currents flowing
through them.
The best way to do this is to layout CIN and COUT near the
device with short traces to the VIN, VOUT, and ground pins.
The regulator ground pin should be connected to the
external circuit ground so that the regulator and its
capacitors have a “single point ground”.
It should be noted that stability problems have been seen
in applications where “vias” to an internal ground plane
were used at the ground points of the device and the
input and output capacitors. This was caused by varying
ground potentials at these nodes resulting from current
flowing through the ground plane. Using a single point
ground technique for the regulator and it's capacitors fixed
the problem. Since high current flows through the traces
going into VIN and coming from VOUT, Kelvin connect the
capacitor leads to these pins so there is no voltage drop
in series with the input and output capacitors.
Optimum performance can only be achieved when the
device is mounted on a PC board according to the diagram
below:
www.richtek.com
10
DS9170-11 March 2007
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
