RT8010/A
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main switch
and the synchronous switch. Thus, the series resistance
looking into the LX pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows :
For RT8010/A packages, the Figure 5 of derating curves
allows the designer to see the effect of rising ambient
temperature on the maximum power allowed.
1.6
Four Layers PCB
1.4
1.2
WQFN-16L 3x3
1.0
RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC)
0.8
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to RL
and multiply the result by the square of the average output
current.
WDFN-6L 2x2
0.6
0.4
0.2
0.0
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
0
25
50
75
100
125
(°C)
Ambient Temperature
Figure 5. Derating Curves for RT8010/APackage
Thermal Considerations
Checking Transient Response
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
PD(MAX) = ( TJ(MAX) - TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8010/ADC/DC converter, where TJ(MAX) is the maximum
junction temperature of the die and TA is the maximum
ambient temperature. The junction to ambient thermal
resistance θJA is layout dependent. For WDFN-6L 2x2
packages, the thermal resistance θJA is 165°C/W on the
standard JEDEC 51-7 four layers thermal test board.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8010/A.
` For the main current paths as indicated in bold lines in
Figure 6, keep their traces short and wide.
The maximum power dissipation at TA = 25°C can be
` Put the input capacitor as close as possible to the device
calculated by following formula :
pins (VINandGND).
PD(MAX) = (125°C − 25°C) / 165°C/W = 0.606W for
WDFN-6L 2x2 packages
`LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT8010/A.
www.richtek.com
12
DS8010/A-02 March 2007
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
