RT8005
Output Capacitor Selection
L1
RT8005
PVDD
The capacitor’ s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’ s edge. Typically, if the ESR requirement is
satisfied, the capacitance is adequate to filtering. The
output ripple voltage can be calculated as :
2, 3
R3
1
6
V
V
IN
LX
OUT
R1
R2
4
VDD
FB
COMP
PGND
R5
C1
C3
7
5
8
C2
9, 10
EN
GND
R4
C4
1
V
DVOUT = DIC (ESR +
)
IN
8 x COUT x fOSC
Where fOSC = operating frequency, COUT = output
capacitance and DIC = DIL = ripple current in the inductor.
Figure 1
The ceramic capacitor with low ESR value provides the
low output ripple and low size profile. Connect a
2.2mF/4.7mF ceramic capacitor at output terminal for good
performance and place the input and output capacitors as
close as possible to the device.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8005.
1. For the main current paths as indicated in bold lines in
Figure 1, keep their traces short and wide.
2. Put the input capacitor as close as possible to the device
pins (PVDD and PGND).
Figure 2. Top Layer
3. LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
4. Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback components
near the RT8005.
5.Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.
6. An example of 2-layer PCB layout is shown in Figure 2
to Figure 3 for reference.
Figure 3. Bottom Layer
www.richtek.com
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DS8005-08 August 2007
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
