RT8003
L1
Output Capacitor Selection
V
OUT
LX
FB
The capacitor’ s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’ s edge. Typically, if the ESR requirement is
satisfied, the capacitance is adequate to filtering. The
output ripple voltage can be calculated as:
V
VDD
EN
IN
R1
R2
RT8003
R4
C3
COMP
GND
C2
C1
1
DVOUT = DIC (ESR +
)
8 x COUT x fOSC
Figure 1
Where fOSC = operating frequency, COUT = output
capacitance and DIC = DIL = ripple current in the inductor.
The ceramic capacitor with low ESR value provides the
low output ripple and low size profile. Connect a 1mF/2.2mF
ceramic capacitor at output terminal for good performance
and place the input and output capacitors as close as
possible to the device.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8003.
1. For the main current paths as indicated in bold lines in
Figure 1, keep their traces short and wide.
Figure 2. Top Layer
2. Put the input capacitor as close as possible to the device
pins (VDD andGND).
3. LX node is with high frequency voltage swing and should
be kept small area. Keep analog components away from
LX node to prevent stray capacitive noise pick-up.
4. Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback components
near the RT8003.
5.Connect all analog grounds to a command node and
then connect the command node to the power ground
behind the output capacitors.
6. An example of 2-layer PCB layout is shown in Figure 2
to Figure 3 for reference.
Figure 3. Bottom Layer
www.richtek.com
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DS8003-08 March 2011
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
