RT7339P
The
RT7339P
needs
no
shunt
regulator
and
signals are detected during the t
S(MIN)
interval and no
valley is detected after the end of the t
S(MIN)
interval,
the next PWM signal will be triggered automatically at
the end of the t
S(MIN)
+ 5s (typ.).
Valley
Signal
PWM
V
DS
V
IN
opto-coupler at the secondary side to achieve the
output voltage regulation. Figure 3 shows several key
waveforms of a conventional flyback converter in
Quasi-Resonant (QR) mode, in which V
AUX
is the
voltage on the auxiliary winding of the transformer.
t
START
Valley
Signal
PWM
t
S(MIN)
Valley
Signal
PWM
t
S(MIN)
0
GD
(V
GS
)
V
AUX
0
(V
OUT
+ V
F
) x N
A
/ N
S
V
IN
x N
A
/ N
P
Clamped by Controller
I
Q1
I
DOUT
Valley
Signal
PWM
t
S(MIN)
5μs
Figure 3. Key Waveforms of a Flyback Converter
Voltage Clamping Circuit
The RT7339P provides a voltage clamping circuit at
DMAG pin since the voltage on the auxiliary winding is
negative when the main switch is turned on. The lowest
voltage on DMAG pin is clamped near zero to prevent
the IC from being damaged by the negative voltage.
Meanwhile, the sourcing DMAG current (I
DMAG
),
flowing through the upper resistor (R
DMAG1
), is
sampled and held to be a line-voltage-related signal for
input over / under voltage protection.
Quasi-Resonant Operation
Figure 4 illustrates how valley signal triggers PWM. If
no valley signal is detected for a long time, the next
PWM is triggered by a starter circuit at the end of the
interval (t
START
, 31.9s typ.). A blanking time (t
S(MIN)
,
8.5μs typ.), which starts at the rising edge of the
previous PWM signal, limits minimum switching period.
When the t
S(MIN)
interval is on-going, all of valley
signals are not allowed to trigger the next PWM signal.
After the end of the t
S(MIN)
interval, the coming valley
will trigger the next PWM signal. If one or more valley
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
Figure 4. PWM Triggered Method
Transconductance Error Amplifier
The RT7339P implements the transconductance error
amplifier with non-linear Gm design to regulate the
Flyback output voltage and provide the fast dynamic
response. The transconductance value is 20A/V at
normal operation. When the voltage detected by the
knee detector at the DMAG pin is higher than 2.75V or
lower than 2.25V, the output of the error amplifier will
source or sink 20uA (typ.) maximum current at the
COMP pin, respectively. As shown in Figure 5, the
non-linear Gm design can provide the fast response for
the dynamic load of PFC converters even though the
bandwidth of the control loop is lower than the line
frequency.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS7339P-03
�½�
�½�
�½�
�½�
August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
