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RT7294AGJ6F 参数 Datasheet PDF下载

RT7294AGJ6F图片预览
型号: RT7294AGJ6F
PDF下载: 下载PDF文件 查看货源
内容描述: [IC REG BCK ADJ 2.5A SYNC SOT23-6]
分类和应用:
文件页数/大小: 14 页 / 326 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
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RT7294A  
2.0  
1.6  
1.2  
0.8  
0.4  
0.0  
maximum power dissipation can be calculated by the  
following formula :  
Four-Layer PCB  
PD(MAX) = (TJ(MAX) TA) / θJA  
where TJ(MAX) is the maximum junction temperature, TA is  
the ambient temperature, and θJA is the junction to ambient  
thermal resistance.  
For recommended operating condition specifications, the  
maximum junction temperature is 125°C. The junction to  
ambient thermal resistance, θJA, is layout dependent. For  
TSOT-23-6 (FC) package, the thermal resistance, θJA, is  
70°C/W on a standard four-layer thermal test board. The  
maximum power dissipation at TA = 25°C can be calculated  
by the following formula :  
0
25  
50  
75  
100  
125  
Ambient Temperature (°C)  
Figure 7. Derating Curve of Maximum PowerDissipation  
PD(MAX) = (125°C 25°C) / (70°C/W) = 1.429W for  
TSOT-23-6 (FC) package  
Layout Considerations  
For best performance of the RT7294A, the following layout  
guidelines must be strictly followed.  
The maximum power dissipation depends on the operating  
ambient temperature for fixed TJ(MAX) and thermal  
resistance, θJA. The derating curve in Figure 7 allows the  
designer to see the effect of rising ambient temperature  
on the maximum power dissipation.  
Input capacitor must be placed as close to the IC as  
possible.  
SW should be connected to inductor by wide and short  
trace. Keep sensitive components away from this trace.  
SW should be connected to inductor by Wide and  
short trace. Keep sensitive components away from  
this trace. Suggestion layout trace wider for thermal.  
C
OUT  
V
OUT  
Keep sensitive components away  
from this trace. Suggestion layout  
trace wider for thermal.  
C
OUT  
GND  
SW  
C
S*  
R
S*  
Suggestion layout trace  
wider for thermal.  
BOOT  
GND  
FB  
6
5
4
SW  
VIN  
EN  
C
C
IN  
IN  
2
3
R
EN  
V
IN  
Input capacitor must be placed as close  
to the IC as possible. Suggestion layout  
trace wider for thermal.  
V
OUT  
R1  
R2  
The R component must  
EN  
The feedback components must be  
connected as close to the device as  
possible.  
be connected to V  
Suggestion layout trace  
wider for thermal.  
.
IN  
Figure 8. PCB Layout Guide  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS7294A-05 October 2016  
www.richtek.com  
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