RT7285/A
2.0
1.6
1.2
0.8
0.4
0.0
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Four-Layer PCB
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
T/SOT-23-6
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOT-23-6 / TSOT-23-6 package, the thermal resistance,
θJA, is 160°C/W on a standard four-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum PowerDissipation
Layout Considerations
PD(MAX) = (125°C − 25°C) / (160°C/W) = 0.625W for
For best performance of the RT7285/A, the following layout
guidelines must be strictly followed.
SOT-23-6 / TSOT-23-6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 7 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Input capacitor must be placed as close to the IC as
possible.
SW should be connected to inductor by wide and short
trace. Keep sensitive components away from this trace.
SW should be connected to inductor by Wide and
short trace. Keep sensitive components away from
this trace. Suggestion layout trace wider for thermal.
C
OUT
V
OUT
Keep sensitive components away
from this trace. Suggestion layout
trace wider for thermal.
C
OUT
GND
C
SW
C
S*
R
S*
Suggestion layout trace
wider for thermal.
BOOT
GND
FB
6
5
4
SW
VIN
EN
C
IN
IN
2
3
R
EN
V
IN
Input capacitor must be placed As close
to the IC as possible. Suggestion layout
trace wider for thermal.
V
OUT
R1
R2
The R component must
EN
The feedback components must be
connected as close to the device as
possible.
be connected to V
Suggestion layout trace
wider for thermal.
.
IN
Figure 8. PCB Layout Guide
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7285/A-03 March 2018
www.richtek.com
13
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