RT7273
Parameter
Current Limit CH 1
Symbol
I
OC_CH1
Test Conditions
R
LIM1
= 37k
R
LIM1
= 50k
R
LIM1
= 63k
R
LIM2, LIM3
= 44k
Current Limit CH 2, CH 3
I
OC_CH2, CH3
R
LIM2, LIM3
= 69k
R
LIM2, LIM3
= 94k
Regulation
Line Regulation
Load Regulation
Error Amplifier
Error Amplifier
Transconductance
Comp to Current Sense
Transconductance
G
EA
G
CS
--
--
250
4
--
--
A/V
A/V
V
IN
= 4.5V to 18V, I
OUT
= 1000mA
I
OUT
= 10% to 90%, I
OUT_MAX
--
--
0.5
0.5
--
--
%V
OUT
%V
OUT
/A
Min
2.4
3.4
4.25
1.6
2.55
3.4
Typ
3
4
5
2
3
4
Max
--
--
--
--
--
--
A
A
Unit
Power Good Reset Generator
Output Falling (device will be
disabled after t
ON_HICCUP
)
Output Rising (PGOOD will be
asserted)
Each Channel Buck
V
UV_CHx
asserted
All Bucks disable during
t
OFF_HICCUP
before re-start is
attempted.
Power good delay time after all
bucks power-up successfully
--
--
--
--
--
--
85
90
10
10
15
640
--
%
--
--
--
--
--
ms
ms
ms
ms
Under-Voltage Threshold
V
UV_CHx
Under-Voltage Deglitch
Time
Hiccup Mode On-Time
Hiccup Mode Off-Time
Power Good
Thermal Shutdown
Thermal Shutdown
Threshold
Thermal Shutdown
Hysteresis
t
UV_DEGLITCH
t
ON_HICCUP
t
OFF_HICCUP
t
PGOOD
T
SD
T
SD
--
--
150
20
--
--
°C
°C
Note 1.
Stresses beyond those listed
“Absolute
Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2.
θ
JA
is measured at T
A
= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
θ
JC
is
measured at the exposed pad of the package.
Note 3.
Devices are ESD sensitive. Handling precaution is recommended.
Note 4.
The device is not guaranteed to function outside its operating conditions.
Copyright
©
2014 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS7273-04
October 2014