RT7271A
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Generally, selecting an
input capacitor with voltage rating 1.5 times greater than
the maximum input voltage is a conservatively safe design.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
V
V
V
OUT
V
IN
⎛
⎝
⎞
⎟
⎠
OUT
I
= I
×
× 1−
IN_RMS
LOAD
⎜
IN
The next step is selecting a proper capacitor for RMS
current rating.Agood design uses more than one capacitor
with low equivalent series resistance (ESR) in parallel to
form a capacitor bank.
Power Good Output (PGOOD)
PGOOD is an open-drain output and requires a pull-up
resistor. PGOODis actively held low in soft-start, standby,
and shutdown. It is released when the output voltage rises
above 90% of nominal regulation point. The PGOOD signal
goes low if the output is turned off or VOUT under 85% of
setting.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
IOUT(MAX) × VOUT
ΔV
=
IN
CIN ×fSW × V
IN
For example, if IOUT_MAX = 6A, CIN = 22μF, fSW = 500kHz,
VIN = 12V and VOUT = 1.05V, the input voltage ripple will
be 47.7mV.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. Both high side and low side gate drivers
will be forced to low if the output is less than 50% of its
set voltage threshold. The UVP will be ignored for at least
1.5ms (typ.) after start up or a rising edge on the EN
threshold. Remove the UVP fault latch by reseting the
EN pin and VIN to restart the controller.
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the Buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
Over Voltage Protection (OVP)
1
⎛
⎝
⎞
⎟
⎠
VP_P = LIR×ILOAD(MAX) × ESR +
⎜
The RT7271A is latched once OVP is triggered and can
only be released by toggling EN threshold or cycling VIN.
There is a 20μs delay built into the over voltage protection
circuit to prevent false transition.
8×COUT ×fSW
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG
)
Over Current Protection (OCP)
can be calculated by the following equation :
The RT7271A provides over current protection by detecting
high side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold
(12A typ.), the OCP will be triggered. When OCP is tripped,
the RT7271A will keep the over current threshold level
until the over current condition is removed.
VSAG = ΔILOAD ×ESR
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7271A-00 February 2013
www.richtek.com
11
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