RT7263B
10µs
2ms
R
EN
100k
V
EN
RT7263B
GND
IN
VIN
Q1
EN
EN/SYNC
VCC
VOUT
Figure 4. Digital Enable Control Circuit
The chip starts to operate when VIN rises to 4.2V (UVLO
threshold). During the VIN rising period, if an 8V output
voltage is set, VIN is lower than the VOUT target value and
it may cause the chip to shut down. To prevent this
situation, a resistive voltage divider can be placed between
the input voltage and ground and connected to the ENpin
to adjust enable threshold, as shown in Figure 5. For
example, the setting VOUT is 8V and VIN is from 0V to
12V, when VIN is higher than 10V, the chip is triggered to
enable the converter. Assume REN1 = 50kΩ. Then,
CLK
External CLK
Figure 6. Startup Sequence Using External Sync Clock
Figure 6 shows the synchronization operation in startup
period. When the EN/SYNC is triggered by an external
clock, the RT7263B enters soft-start phase and the output
voltage starts to rise. During the soft-start phase region,
the oscillation frequency will be proportional to the feedback
voltage until it is higher than 0.7V. With higher VFB, the
switching frequency is relatively higher. After startup period
about 2ms, the IC operates with the same frequency as
the external clock.
(R
(V
x V
)
)
EN1
IH(MIN)
R
EN2
=
− V
IN_S
IH(MIN)
where VIH(MIN) is the minimum threshold of enable rising
(2V) and VIN_S is the target turn on input voltage (10V in
this example). According to the equation, the suggested
resistor R EN2 is 12.5kΩ.
Output Under Voltage Protection (Hiccup Mode)
For the IC, Hiccup Mode of Under Voltage Protection (UVP)
is provided. When the FB voltage drops below half of the
feedback reference voltage, VFB, the UVP function will be
triggered and the IC will shut down for a period of time and
then recover automatically. The Hiccup Mode of UVP can
reduce input current in short-circuit conditions.
R
EN1
V
IN
EN
R
EN2
RT7263B
GND
Inductor Selection
Figure 5. ResistorDivider for Lockout Threshold Setting
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
Operating Frequency and Synchronization
The internal oscillator runs at 500kHz (typ.) when the EN/
SYNC pin is at logic-high level (>2V). If the EN pin is
pulled to low-level for 10μs above, the IC will shut down.
The RT7263B can be synchronized with an external clock
ranging from 300kHz to 2MHz applied to the EN/SYNC
pin. The external clock duty cycle must be from 30% to
90%.
V
f ×L
VOUT
V
IN
⎡
OUT ⎤ ⎡
× 1−
⎥ ⎢
⎤
ΔIL =
⎢
⎣
⎥
⎦
⎦ ⎣
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Highest efficiency operation is achieved by reducing
ripple current at low frequency, but it requires a large
inductor to attain this goal.
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7263B-01 September 2012
www.richtek.com
11
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
