RT7205A
Parameter
Symbol
VOL_VG_INI
RGS_LOW
Conditions
Min
--
Typ
--
Max
1
Unit
V
Initial Output Low Clamping
Voltage before Start-up
VDD = 2.5V, ISINK = 50mA
Internal Pull-Low Resistor
V_TR Section
--
20
--
kΩ
V_TR Internal Resistance
RVDS2
4.56
--
4.80
5
5.04
--
kΩ
(|VV_TR_HIGH
VV_TR_HIGH) x 100
-
SH| /
VVTR_
V_TR Sample and Hold Error
ESH_VTR
%
V_TR Sample and Hold
Threshold
VTH_SH = KVTR_SH
VV_TR_HIGH[n-1]
x
KVTR_SH
tMASK
--
0.875
--
--
Mask Time
VV_TR > VTH_SH
--
300
0.5
--
ns
000
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0.7
0.9
1.1
Register-Programmable V_TR
Blanking Time
VV_TR > VTH_SH
(Note 5)
µs
tBLANK_ VTR
1.3
1.5
1.7
1.9
Disable
0.4
0.3
0.25
0.2
0.5
0.45
0.4
0.35
0.3
If VV_TR_HIGH - (VOUT
x
>
)
,
Register-Programmable V_TR
Under Voltage Threshold
KVDS_SR
VTH_VTR_UV
SR driver is active.
V
VTH_VTR_UV
0.15
0.1
0.25
0.2
0.35
0.3
0.05
0
0.15
0.1
0.25
0.2
When VV_TR < KVIN_LOW
VOUT, It will send an
interrupt to MCU.
x
Low Level Threshold for Input
Voltage
KVIN_LOW
2.0
2.8
2.2
3.0
2.4
3.2
--
V
VTH_VTR_OV
V_TR Over-Voltage Threshold
V9 = 4.5V
Low Level Threshold for V_TR
Falling Edge Detection and
Dead Time Comparison
Threshold
VTH_VTR_DT
V
0.05
0.10
0.15
Dead Time Comparator Delay
tD_DT
(Note 5)
--
--
--
40
--
ns
ns
Disable dead time
comparator on VG rising
edge
Dead Time Comparator
Blanking Time
tBLANK_DT
700
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7205A-00 February 2018
www.richtek.com
13
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