RT7080
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Four-Layer PCB
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve of Maximum PowerDissipation
Layout Considerations
Decoupling Cap. of V5D
must be placed close to
RT7080, The GND path
connected to PGND by
a short trace.
PGND
DGND
DGND
The GND of FB (Pin34)
must be connected to
DGND to avoid the
ground bounce.
C
SWGND (Pin33) must
be connected to PGND
by a short trace.
DGND
R
V1P8N (Pin4) must be
connected to V5VN
(Pin6) by a single and
short trace.
C
C
VILDO
NC
PGND
PGND
W
C
P0_11
Decoupling Cap. Of
VILDO must be close to
RT7080.
RSTN
NC
V1P8N
V1P8
V5VN
V5V
W
V
W
SWGND, FB, V5D cap.
& DGND direct
connected to PGND
(Pin27, 28) by a wide
trace.
V
5V
Decoupling Cap. of V5V
and V1P8, must be
placed close to RT7079.
V
AD9
C
C
C
U
AD8
U
U
AD7
GND
CVIN (high frequency
non-inductive capacitor)
must be close to VIN &
PGND pin by wide &
short trace.
C
C
C
Charge pump Cap.
(CPN, CPP, VCP) must
be placed close to
RT7080.
VIN
VIN
AGND
Figure 3. PCB Layout Guide with Buck
Copyright 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
©
DS7080-00 August 2019
www.richtek.com
13
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