RT6340
delay elapsed. When V
FB
falls below power-good low
threshold (V
TH_PGHL2
) (92% of the reference voltage,
typically) or exceeds V
TH_PGHL1
(109% of the reference
voltage, typically), the PGOOD pin will be pulled low. For
V
FB
higher than V
TH_PGHL1
, V
PGOOD
can be pulled high
again if V
FB
drops back by a power-good high threshold
(V
TH_PGLH2
) (106% of the reference voltage, typically).
Once being started-up, if any internal protection is
triggered, PGOOD will be pulled low to GND. The internal
open-drain pull-down device (6Ω, typically) will pull the
PGOOD pin low. The power good indication profile is shown
in Figure 2.
V
TH_PGHL1
V
TH_PGLH2
V
TH_PGLH1
V
TH_PGHL2
V
FB
certain amount of delay when the high-side MOSFET
being turned on. If an over-current condition occurs, the
converter will immediately turn off the high-side MOSFET
to prevent the inductor current exceeding the high-side
MOSFET peak current limit (I
LIM
).
Output Under-Voltage Protection
The RT6340 includes output under-voltage protection
(UVP) against over-load or short-circuited condition by
constantly monitoring the feedback voltage V
FB
. If V
FB
drops below the under-voltage protection trip threshold
(50% of the internal reference voltage, typically), the UV
comparator will go high to turn off the internal high-side
switch. If the output under-voltage condition continues for
a period of time, the RT6340 enters output under-voltage
protection with hiccup mode and discharges the C
SS/TR
by an internal discharging current source I
SS_DIS
(0.5μA,
typically). During hiccup mode, the device remains
shutdown. After the SS pin voltage is discharged to less
than 54mV (typically), the RT6340 attempts to re-start up
again, and the internal charging current source I
SS
(2μA,
typically) gradually increases the voltage on C
SS/TR
. The
high-side MOSFET will start switching when voltage
difference between SS pin and FB pin is larger than 75mV
( i.e. V
SS
−
V
FB
> 75mV, typically). If the output under-
voltage condition is not removed, the high-side MOSFET
stops switching when the voltage difference between SS
pin and FB pin is 1.2V ( i.e. V
SS
−
V
FB
= 1.2V, typically)
and then the I
SS_DIS
discharging current source begins to
discharge C
SS/TR
. Upon completion of the soft-start
sequence, if the output under-voltage condition is removed,
the converter will resume normal operation; otherwise, such
cycle for auto-recovery will be repeated until the output
under-voltage condition is cleared. Hiccup mode allows
the circuit to operate safely with low input current and
power dissipation, and then resume normal operation as
soon as the over-load or short-circuit condition is removed.
Since the C
SS/TR
will be discharged to 54mV when the
RT6340 enters output under-voltage protection, the first
discharging time (t
SS_DIS1
) can be calculated as below :
V
PGOOD
Figure 2. The Logic of PGOOD for RT6340GQW
Input Under-Voltage Lockout
In addition to the EN pin, the RT6340 also provides enable
control through the VIN pin. If V
EN
rises above V
TH_EN
first,
the switching will be inhibited until the VIN voltage rises
above V
UVLOH
. It is to ensure that the internal regulator is
ready so that operation with not-fully-enhanced internal
high-side MOSFET can be prevented. After the device is
powered up, if the input voltage V
IN
goes below the UVLO
falling threshold voltage (V
UVLOL
), this switching will be
inhibited; if V
IN
rises above the UVLO rising threshold
(V
UVLOH
), the device will resume switching. Note that V
IN
= 4V is only design for input voltage momentarily falls
down to the UVLO threshold voltage requirement, and
normal input voltage should be larger than the V
UVLOH
.
High-Side MOSFET Peak Current Limit Protection
The RT6340 includes a cycle-by-cycle high-side MOSFET
peak current-limit protection against the condition that
the inductor current increasing abnormally, even over the
inductor saturation current rating. The inductor current
through the high-side MOSFET will be measured after a
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
V
0.054
t
SS_DIS1
= C
SS
SS
I
SS_DIS
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS6340-00
September 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
