RT6296B
The inductor's current rating (caused
a
40C
current rating and long term reliability considerations.
Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead
to significant ringing.
temperature rising from 25C ambient) should be
greater than the maximum load current and its
saturation current should be greater than the short
circuit peak current limit.
CIN and COUT Selection
Thermal Considerations
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the top MOSFET.
To prevent large ripple current, a low ESR input
capacitor sized for the maximum RMS current should
be used. The RMS current is given by :
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
V
V
IN
OUT
I
I
OUT(MAX)
1
RMS
V
IN
V
OUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief.
PD(MAX) = (TJ(MAX) TA) / JA
where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and JA is the junction to
ambient thermal resistance.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. The
selection of COUT is determined by the required
Effective Series Resistance (ESR) to minimize voltage
ripple. Moreover, the amount of bulk capacitance is
also a key for COUT selection to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later
section. The output ripple, VOUT, is determined by :
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For TSOT-23-8 (FC) package, the thermal
resistance, JA, is 70C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25C can be calculated by the
following formula :
PD(MAX) = (125C 25C) / (70C/W) = 1.428W for
TSOT-23-8 (FC) package
1
V
I ESR
L
OUT
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure 3
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
8fC
OUT
The output ripple will be highest at the maximum input
voltage since IL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet
the ESR and RMS current handling requirement. Dry
tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low
ESR value. However, it provides lower capacitance
density than other types. Although Tantalum capacitors
have the highest capacitance density, it is important to
only use types that pass the surge test for use in
switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR. However, it
can be used in cost-sensitive applications for ripple
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DS6296B-02 June 2016
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