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RT6222D 参数 Datasheet PDF下载

RT6222D图片预览
型号: RT6222D
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用:
文件页数/大小: 15 页 / 366 K
品牌: RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
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RT6222C/D  
Feed-forward Capacitor (Cff)  
Enable Operation (EN)  
The RT6222C/Dis optimized for ceramic output capacitors  
and for low duty cycle applications. However for high-output  
voltages, with high feedback attenuation, the circuit's  
response becomes over-damped and transient response  
can be slowed. In high-output voltage circuits (VOUT > 3.3V)  
transient response is improved by adding a small feed-  
forwardcapacitor (Cff) across the upper FB divider resistor  
(figure 1), to increase the circuit's Q and reduce damping  
to speed up the transient response without affecting the  
steady-state stability of the circuit. Choose a suitable  
capacitor value that following below step.  
For automatic start-up the EN pin can be connected to  
VIN, through a 100kΩ resistor. Its large hysteresis band  
makes EN useful for simple delay and timing circuits. EN  
can be externally pulled to VIN by adding a resistor-  
capacitor delay (REN and CEN in Figure 2). Calculate the  
delay time using EN's internal threshold where switching  
operation begins (1.5V, typical).  
An external MOSFET can be added to implement digital  
control of EN when no system voltage above 2V is available  
(Figure 3). In this case, a 100kΩ pull-up resistor, REN, is  
connected between VINand the ENpin. MOSFET Q1 will  
be under logic control to pull down the ENpin. To prevent  
enabling circuit when VINis smaller than the VOUT target  
value or some other desired voltage level, a resistive voltage  
divider can be placed between the input voltage and ground  
and connected to EN to create an additional input under  
voltage lockout threshold (Figure 4).  
Get the BW the quickest method to do transient  
response form no load to full load. Confirm the damping  
frequency. The damping frequency is BW.  
EN  
R
BW  
EN  
V
EN  
RT6222C/D  
IN  
C
EN  
GND  
V
OUT  
Figure 2. External Timing Control  
R1  
C
ff  
R
100k  
EN  
FB  
RT6222C/D  
V
IN  
EN  
RT6222C/D  
GND  
R2  
Q1  
Enable  
GND  
Figure 1. Cff Capacitor Setting  
Figure 3. Digital Enable Control Circuit  
Cff can be calculated base on below equation :  
1
Cff  
23.1412R1BW 0.8  
R
EN1  
V
IN  
EN  
R
EN2  
RT6222C/D  
GND  
Figure 4. ResistorDivider for Lockout Threshold Setting  
Copyright 2018 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
12  
DS6222C/D-02 August 2018