RT6206B
Functional Block Diagram
VINR*
VREG5
BOOT
EN
POR &
Reg
VBIAS
OC
UV & OV
V
REG5
6µA
V
REF
Min.
Off-Time
VREG5
VIN
SW
Control
Driver
SW
Ripple
Gen.
FB
+
+
-
Comparator
ZC
PGND
GND*
SS
V
IN
FB
On-Time
Comparator
FB
0.9 x V
REF
-
+
PGOOD*
* : VINR, GND pin for TSSOP-14 (Exposed Pad) only.
* : PGOOD pin for TSSOP-14 (Exposed Pad) and WDFN-10L 3x3 only.
Operation
The RT6206B is a synchronous step-down converter with
advanced constant on-time control mode. Using the
ACOT
TM
control mode can reduce the output capacitance
and provide fast transient response. It can minimize the
component size without additional external compensation
network.
Internal Regulator
The regulator provides 5.1V power to supply the internal
control circuit. Connecting a 1μF ceramic capacitor for
decoupling and stability is required.
Soft-Start
In order to prevent the converter output voltage from
overshooting during the startup period, the soft-start
function is necessary. The soft-start time is adjustable
and can be set by an external capacitor.
UVLO Protection
To protect the chip from operating at insufficient supply
voltage, the UVLO is needed. When the input voltage of
VIN is lower than the UVLO falling threshold voltage, the
device will be latch-off.
Thermal Shutdown
When the junction temperature exceeds the OTP
threshold value, the IC will shut down the switching
operation. Once the junction temperature cools down and
is lower than the OTP lower threshold, the converter will
automatically resume switching
Power Good (for TSSOP-14 (Exposed Pad) and
WDFN-10L 3x3 only)
After soft-start is finished, the power good function will be
activated. When the FB is activated, the PGOOD will
become an open-drain output. If the FB is below, the
PGOOD pin will be pulled low.
Copyright
©
2017 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS6206B-02 March 2017
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
