RT5710A
X7R ceramic capacitors are usually selected for power
regulator capacitors because the dielectric material has
less capacitance variation and more temperature
stability.
Another parameter that has influence on the output
voltage sag is the equivalent series inductance (ESL).
The rapid change in load current results in di/dt during
transient. Therefore, the ESL contributes to part of the
voltage sag. Using a capacitor with low ESL can obtain
better transient performance. Generally, using several
capacitors connected in parallel can have better
transient performance than using a single capacitor for
the same total ESR.
Voltage rating and current rating are the key
parameters when selecting an input capacitor.
Generally, selecting an input capacitor with voltage
rating 1.5 times greater than the maximum input
voltage is a conservatively safe design.
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using
the following equation :
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
V
V
V
OUT
V
IN
OUT
I
= I
1
IN_RMS
LOAD
IN
The next step is selecting a proper capacitor for RMS
current rating. One good design uses more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor bank.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
PD(MAX) = (TJ(MAX) TA) / JA
where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and JA is the
junction-to-ambient thermal resistance.
IOUT(MAX)
C fSW
IN
VOUT
V
IN
VOUT
V
IN
V
=
1
IN
For continuous operation, the maximum operating
junction temperature indicated under Recommended
Operating Conditions is 125C. The junction-to-ambient
thermal resistance, JA, is highly package dependent.
For WDFN-6L 2x2 package, the thermal resistance, JA,
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the Buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
is 120C/W on
a
standard JEDEC 51-7 high
effective-thermal-conductivity four-layer test board. The
maximum power dissipation at TA = 25C can be
calculated as below :
1
VP_P = LIRILOAD(MAX) ESR +
8COUT fSW
PD(MAX) = (125C 25C) / (120C/W) = 0.833W for a
WDFN-6L 2x2 package.
When load transient occurs, the output capacitor
supplies the load current before the controller can
respond. Therefore, the ESR will dominate the output
voltage sag during load transient. The output voltage
undershoot (VSAG) can be calculated by the following
equation :
The maximum power dissipation depends on the
operating ambient temperature for the fixed TJ(MAX)
and the thermal resistance, JA. The derating curve in
Figure 2 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.
VSAG = ILOAD ESR
For a given output voltage sag specification, the ESR
value can be determined.
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DS5710A-04 November 2019
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