RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
Buck over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Buck OCP event detected
BUCK_
OCP_EVT
7
0
0
0
0
0
0
RC
RC
RC
RC
RC
RC
RC
LDO1 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO1 OCP event detected
LDO1_
OCP_EVT
6
5
4
3
2
1
LDO2 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO2 OCP event detected
LDO2_
OCP_EVT
LDO3 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO3 OCP event detected
LDO3_
OCP_EVT
0x17
OCP_EVT
LDO4 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : LDO4 OCP event detected
LDO4_
OCP_EVT
Boost over-current protection acknowledgement.
(raising trigger )
0 : No fault or be masked (default)
1 : Boost OCP event detected
BOOST_
OCP_EVT
Buck2 over-current protection acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Buck2 OCP event detected
BUCK2_
OCP_EVT
0
0
0
Reserved
RC Reserved
Addr
RegName
Bit
BitName
Default Type
Description
Thermal warning sense acknowledgement.
(raising/falling trigger)
0 : No fault or be masked (default)
1 : Thermal warning event detected
TWARN_
EVT
7
6
5
4
0
0
0
RC
RC
RC
RC
Thermal shutdown sense acknowledgement.
(raising/falling trigger)
0 : No fault or be masked (default)
1 : Thermal shutdown event detected
TSD_EVT
VSYS under-voltage sense acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Under-voltage event detected
0x19 BASE_EVT
VSYSUV_
EVT
VSYS over-voltage sense acknowledgement.
(raising trigger)
0 : No fault or be masked (default)
1 : Over-voltage event detected
VSYSOV_
EVT
0
3:0 Reserved
0000
RC Reserved
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
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