RT5035C/D
Parameter
SCLK Clock Rate
Symbol
fSCL
Test Conditions
Min
Typ
Max Unit
VDDM = 3.1V, VOUT2 = 3.3V
--
--
400
kHz
Hold Time (Repeated) START
condition.
After this Period, the First Clock
Pulse is Generated
tHD;STA
0.6
--
--
s
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
tLOW
1.3
0.6
--
--
--
--
s
s
tHIGH
Set-up Time for a Repeated
START Condition
tSU;STA
0.6
--
--
s
Data Hold Time
tHD;DAT
tSU;DAT
0
--
--
--
0.9
--
s
ns
s
Data Set-Up Time
100
0.6
Set-Up Time for STOP Condition tSU;STO
--
Bus Free Time between a STOP
tBUF
1.3
20
20
2
--
--
--
--
--
s
ns
and START Condition
Rise Time of both SDA and SCL
Signals
tR
300
300
--
Fall Time of both SDA and SCL
Signals
tF
ns
SDA and SCL Output Low Sink
Current
IOL
SDA or SCL voltage = 0.4V
mA
Output Voltage Ramp Rate
VOUT1 Ramp Rate
VOUT2 Ramp Rate
VOUT3 Ramp Rate
VOUT4 Ramp Rate
VOUT5 Ramp Rate
VOUT6 Ramp Rate
VOUT8 Ramp Rate
VOUT10 Ramp Rate
VOUT1 = 3.6V to 5.3V
VOUT2 = 0V to 3.25V
VOUT3 = 0V to 1.1V
VOUT4 = 0V to 1.8V
VOUT5 = 0V to 2.2V
VOUT6 = 0V to 2.7V
VOUT8 = 0V to 3.4V
VOUT10 = 0V to 1.35V
--
--
--
--
--
--
--
--
1.24
0.82
0.33
0.44
0.6
--
--
--
--
--
--
--
--
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
V/ms
0.84
0.84
0.41
Ramp Rate Accuracy of All the
Above
40
--
+40
%
Enabling Delay Time
Delay Time Step Resolution
Off Discharge
For ENDLY2, 3, 4, 10
1.5
2
2.5
ms
VOUT1, 2, 3, 4, 5, 10 Discharge
Equivalent Resistance
VDDM = 3.1V and VOUTx = 1V
VDDM = 3.1V and SWO = 1V
VDDM = 3.1V and VOUT6 = 1V
VDDM = 3.1V and VOUT8 = 1V
50
--
--
--
--
--
--
--
--
SW4 Discharge Equivalent
Resistance
400
200
200
VOUT6 Discharge Equivalent
Resistance
VOUT8 Discharge Equivalent
Resistance
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS5035C/D-01 February 2020
www.richtek.com
13
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