RT4723P
ambient thermal resistance, JA, is highly package
dependent. For a WL-CSP-15B 1.39x2.07 (BSC)
package, the thermal resistance, JA, is 49.8C/W on a
standard JEDEC 51-7 high effective-thermal-
Layout Considerations
For the best performance of the RT4723P, the
following PCB layout guidelines should be strictly
followed.
conductivity four-layer test board. The maximum power
dissipation at TA = 25C can be calculated as below :
For good regulation, place the power components as
close to the IC as possible. The traces should be
wide and short especially for the high current output
loop.
PD(MAX) = (125C 25C) / (49.8C/W) = 2W for a
WL-CSP-15B 1.39x2.07 (BSC) package.
The maximum power dissipation depends on the
operating ambient temperature for the fixed TJ(MAX)
and the thermal resistance, JA. The derating curves in
Figure 2 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.
The input and output bypass capacitor should be
placed as close to the IC as possible and connected
to the ground plane of the PCB.
The flying capacitor should be placed as close to the
C1P/C1N/C2P/C2N pin as possible to avoid noise
injection.
2.5
Four-Layer PCB
Minimize the size of the LXP node and keep the
traces wide and short. Care should be taken to avoid
running traces that carry any noise-sensitive signals
near LXP or high-current traces.
2.0
1.5
1.0
0.5
0.0
Separate power ground (PGND) and analog ground
(GND). Connect the GND and the PGND islands at
a single end. Make sure that there are no other
connections between these separate ground planes.
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve of Maximum Power
Dissipation
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS4723P-00 December 2016
www.richtek.com
13
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
