RT3662EB
Pin No.
14
Pin Name
VCC
Pin Function
Controller power supply. Connect this pin to 5V and place a decoupling
capacitor 2.2F at least. The decoupling capacitor is as close controller as
possible.
System power good input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load-line slope and initial
offset. If PWROK is high, the SVI interface is running and the DAC decodes
the received serial VID codes to determine the output voltage.
Serial VID clock input.
Serial VID data input. This pin is a serial data line.
Serial VID telemetry output from VR. This pin is a push-pull output.
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
Power good indicator for the VDDC controller. This pin is an open drain
output.
VDDC controller voltage sense input. This pin is connected to the terminal of
VDDC controller output voltage.
No internal connection.
Bootstrap supply of phase1 for high side MOSFET. This pin powers high
side MOSFET driver.
Upper gate driver output of phase1. Connect this pin to the gate input of high
side MOSFET.
Switch nodes of high side driver for phase1. Connect this pin to high side
MOSFET Source together with the low side MOSFET Drain and the
inductor.
Lower gate driver output of phase1. Connect this pin to the gate input of low
side MOSFET.
Driver power supply. Connect this pin to GND by the 2.2F ceramic
capacitor at least. The decoupling capacitor is as close controller as
possible.
Lower gate driver output of phase2. Connect this pin to the gate input of low
side MOSFET.
Switch nodes of high side driver for phase2. Connect this pin to high side
MOSFET Source together with the low side MOSFET Drain and the
inductor.
Upper gate driver output of phase2. Connect this pin to the gate input of high
side MOSFET.
Bootstrap supply of phase2 for high side MOSFET. This pin powers high
side MOSFET driver.
Controller enable input pin.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
15
PWROK
16
17
18
19
SVC
SVD
SVT
VDDIO
20
21
22
23
24
PGOOD
VSEN
NC
BOOT1
UGATE1
25
PHASE1
26
LGATE1
27
PVCC
28
LGATE2
29
PHASE2
30
31
32
UGATE2
BOOT2
EN
33 (Exposed Pad) GND
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3662EB-04
August 2019
www.richtek.com
3
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
