RT3661AB
Functional Block Diagram
VSEN_NB
TSEN_NB
VRHOT_L
PWROK
IMONI_NB
IMONI
UVLO
GND
MUX
SVI2 Interface
Configuration Registers
Control Logic
Loop Control
Protection Logic
From Control Logic
ADC
RGND
DAC
ERROR
AMP
AI_VDD, AI_VDDNB
QR_TH
TONSET
OFFSET
PHOCP_TH
PGOOD
VDDIO
VSEN
TSEN
SET1
VCC
SVC
SVD
SVT
EN
Soft Start&
Slew Rate Control
FB
COMP
VSET
+
-
VIN
Offset
Cancellation
+
+
-
PWM
CMP
QR_TH
BOOT
TON
GEN
PWM
Driver
UGATE
PHASE
LGATE
1.867m
ISEN1P
ISEN1N
VREF_PINSET
IMON
+
-
+
-
0.75 x AI_VDD
RAMP
TONSET
IMONI
VSEN
Driver
POR
PVCC
OV/UV
From Control Logic
+
OC
To Protection Logic
VIN
RGND
DAC
VSET_NB
ERROR
AMP
OCP_SPIKE
-
Soft Start&
Slew Rate Control
FB_NB
COMP_NB
+
-
Offset
Cancellation
+
PWM
CMP
PWM
_NB
BOOT_NB
Driver
UGATE_NB
PHASE_NB
LGATE_NB
+
-
TON
GEN
1.867m
TONSET
RAMP
0.75 x AI_VDDNB
+
ISENP_NB
ISENN_NB
+
-
VREF_PINSET
IMON_NB
-
IMONI_NB
VSEN_NB
OV/UV
+
OC_NB
OCP_SPIKE_NB
-
To Protection Logic
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3661AB-05
May
2019
www.richtek.com
5
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