RT2862
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
The output ripple will be the highest at the maximum input
voltage since ∆IL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 6.e)
reduces the θJA to 49°C/W.
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. The Figure 7 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation allowed.
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
2.2
Four-Layer PCB
2.0
1.8
Copper Area
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2
70mm
PD(MAX) = (TJ(MAX) − TA ) / θJA
2
50mm
30mm
2
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
2
10mm
Min.Layout
For recommended operating conditions specification of
RT2862, the maximum junction temperature is 125°C. The
junction to ambient thermal resistance θJA is layout
dependent. For SOP-8 (Exposed Pad) package, the
thermal resistance θJA is 75°C/W on the standard JEDEC
51-7 four-layers thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7.Derating Curve of Maximum PowerDissipation
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
12
DS2862-02 January 2018
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
