RT1730
Addr
Length
RegName
Bit
BitName
Default
Type
Description
0b : When Vconn is enabled, apply it to the CC2
pin.
0x19
1
TCPC_CONTR
OL
0
PLUG_ORIENT
0
RW
Monitor
the
CC1
pin
for
BMC
communications if PD messaging is enabled.
1b : When Vconn is enabled, apply it to the CC1
pin.
Monitor
the
CC2
pin
for
BMC
communications if PD messaging is enabled.
Required
7
Reserved
0
R
0b : No DRP. Bits B3..0 determine Rp/Rd/Ra
6
DRP
0
RW
settings
1b : DRP
00b : Rp default
5:4
RP_VALUE
0
RW
01b : Rp 1.5A
10b : Rp 3.0A
11b : Reserved
0x1A
1
ROLE_CONTR
OL
3:2
CC2
10
RW
00b : Reserved
01b : Rp (Use Rp definition in B5..4)
10b : Rd
11b : Open (dDisconnect or don’t care)
Set to 11b if enabling DRP in B7..6
00b : Reserved
01b : Rp (Use Rp definition in B5..4)
1:0
CC1
10
RW
10b : Rd
11b : Open (dDisconnect or don’t care)
Set to 11b if enabling DRP in B7..6
7
0x1B
1
FAULT_CONTR
OL
0
DIS_VCON_OC
0
RW
DIS_VCON_OV
0
RW
0b : Fault detection circuit enabled
1b : Fault detection circuit disabled
0b : Fault detection circuit enabled
1b : Fault detection circuit disabled
Copyright
©
2018 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS1730-01 January 2018
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
