RT1710
Thermal Considerations
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Four-Layer PCB
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
0
25
50
75
100
125
Ambient Temperature (°C)
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-8L 2x3 package, the thermal resistance, θJA, is
31.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
Figure 3. Derating Curve of Maximum PowerDissipation
Layout Consideration
PCB layout is very important for designing e-marked IC
(RT1710) circuits.
The VCON1 and VCON2 traces should be wide (10mil)
and short especially for the current loop.
PD(MAX) = (125°C − 25°C) / (31.5°C/W) = 3.17W for
WDFN-8L 2x3 package
Connect VCON1/VCON2 pins with bypass capacitor,
and as near the pins as possible.
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
The exposed pad of the chip should be connected to a
large ground plane for thermal consideration.
Keep the CC1 traces away from those sensing pins
(D+, D-, SSTX+, SSTX-, SSRX+, SSRX-, SBU).
Keep the CC1 traces away from those sensing pins
(D+,D-,SSTX+,SSTX-,SSRX+,SSRX-,SBU)
VCONN
(Another side)
RT1710
The VCON1 and VCON2
traces should be wide (10mil)
and short especially for the
current loop.
NC
NC
SCL
VCONN
CC PIN
VCON1
CCIN
Test pad
Test pad
VCON2
GND
0.1µF
SDA
EP
0.1µF
The exposed pad of the chip should be
connected to a large ground plane for
thermal consideration.
Connect VCON1/VCON2 pins
with bypass capacitor,and as
near the pins as possible.
Figure 4. PCB Layout Guide
Copyright 2016 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS1710-00 May 2016
www.richtek.com
13
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