RT8251
to return VOUT to its steady-state value. During this
recovery time, VOUT can be monitored for overshoot or
ringing that would indicate a stability problem.
snubber between SW and GND and make them as close
as possible to the SW pin (see Figure 5). Another method
is to add a resistor in series with the bootstrap capacitor,
CBOOT. But this method will decrease the driving capability
to the high-side MOSFET. It is strongly recommended to
reserve the R-C snubber during PCB layout for EMI
improvement. Moreover, reducing the SW trace area and
keeping the main power in a small loop will be helpful on
EMI performance. For detailed PCB layout guide, please
refer to the section of Layout Consideration.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on the SW pin when
high-side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One is to place an R-C
R
*
BOOT
1
3
2
V
IN
BOOT
RT8251
VIN
4.75V to 24V
C
IN
10µF x 2
C
BOOT
L
4.7µH
100nF
R
*
EN
V
OUT
SW
Chip Enable
3.3V/5A
7
EN
D
R *
S
B540C
C
*
EN
R1
30.9k
C
OUT
22µF x 2
C *
S
8
SS
5
6
FB
C
SS
10nF
4,
C
C
R
C
R2
10k
2.2nF
Exposed Pad(9)
22k
GND
COMP
C
P
* : Optional
NC
Figure 5. Reference Circuit with Snubber and Enable Timing Control
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
PSOP-8
PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for
WQFN
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W for
PSOP-8 (70mm2copper area PCB layout)
PD(MAX) = (TJ(MAX) − TA ) / θJA
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to
increase thermal performance by the PCB layout copper
design. The thermal resistance θJA can be decreased by
adding copper area under the exposed pad of SOP-8
(Exposed Pad) package.
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8251, the maximum junction temperature is 125°C. The
junction to ambient thermal resistance θJA is layout
dependent. For PSOP-8 and WQFNpackages, the thermal
resistance θJA are 75°C/W and 68°C/W on the standard
JEDEC 51-7 four-layers thermal test board. The maximum
power dissipation at TA = 25°C can be calculated by
following formula :
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
Copyright 2013 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8251-04 February 2013
www.richtek.com
11
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